Xilinx-FPGA DNA reading method
Published time: 2020-04-10 10:51:34
Each FPGA of Xilinx has a unique ID, which is Device DNA. This ID is equivalent to our ID card. It has been written in the eFuse register of the chip when the FPGA chip is produced. It has unmodifiable attributes because of the use of It is the fuse technology. It is worth noting that in the 7 series and before, this ID is 57bit, but it is 96bit under Xilinx's Ultraslace architecture.
Our general use scenario for FPGA DNA is for user logic encryption. Generally speaking, the user can logically read this Device DNA through a specific interface, and after a series of encryption algorithms, compare it with a string of encrypted bytes stored in the external Flash in advance. The resulting byte string is also obtained after the DNA is encrypted. After fpga loads the program, it can read the byte from flash for comparison. If it is the same, let the FPGA start the corresponding logic. If it is different, it means that the FPGA does not have With the authorization of the user, the user can logically shut down the logic function of the FPGA or even damage the hardware through some means.
How to get FPGA Device DNA, I will explain the two methods from JTAG and call source language, and open the core code for your reference.
The first one is obtained through JTAG. This method can be implemented in ISE's Impact or vivado. The following describes how to use Vivado or Device DNA. This is actually very simple. First, the board is connected to the PC through JTAG. In Flow Navigator-> PROGRAM Under the AND DEBUG interface, click the corresponding FPGA chip, click Hardware Device Properties, search for dna in the search, you can find Device DNA under REGISTER, and there is a corresponding article on how to obtain DNA under Impact. I will not go into details here.
Second, user logic is obtained by calling the source language. As for what the source language is, here is a tip to share with you. Generally, when we use the source language, we often cannot remember a large number of source language definitions, so how to quickly search for what we want The source language you want, in Vivado, there is a function of Language Templates, which can be found in Flow Navigator, which contains basically all the source language and some grammatical usage provided by Xilinx. Taking DNA reading as an example, we search for DNA, You can find the source language of DNA. Because the blogger uses the VU9P film, the source language of DNA_PORTE2 is used. For the 7 series and before, the source language of DNA_PORT is used. Both source languages can be found in Language Templates found.
Next, let's talk about the use of this source language and the source language. This source language is essentially reading the FUSE_DNA register in the FUSE register table. It also contains a shift register. The interfaces in the source language are essentially operations. Shift register, the length of this shift register depends on the device type, it is 56 or 96bit. The READ signal in the source language is used to load the DNA value into the shift register, DIN is the input of the shift register, DOUT is the output of the shift register, SHIFT is the shift enable of the shift register, and CLK is The operation clock of the shift register, the source language model and timing diagram provided by the official are as follows
For users, to call this source language, we only need to operate according to the process of operating the shift register. Our purpose is to read the value of the shift register in the source language, so our design idea should be to pull up first READ first loads the shift register with the DNA value, and then enables SHIFT on the rising edge of the clock, so that the value in the shift register can be shifted out. The following is the core code:
This is a module of the axis bus. When dna_read_rdy is pulled high, the external is ready to receive data. At this time, the module reads the DNA value and sends it to the external module. When the external module receives the data and the dna_read_vld signal, it dna_read_rdy is pulled down A DNA value transmission process.Tag: FPGA
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