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Using TMS320VC5402 and UDA1341TS converter to realize the design of train voice recording equipment

Update Time: 2020-04-18 17:09:50

Foreword

The train operation monitoring and recording device has played a huge role in the safe transportation of the railway, but the shortcoming is that there is no voice recording function. In order to solve this problem, according to the technical requirements of the Ministry of Railways, this paper researched and developed a new type of train voice recording device. This equipment is mainly used to record the joint control of flight attendants and locomotives, and can cooperate with the monitoring device to analyze driving accidents, providing new technical means for the scientific management of the locomotive department and the transportation department. In view of the technical indicators and standards of common equipment, for the digitization of speech, sampling is performed at a sampling frequency of 16KHz and 16-bit quantization accuracy. In terms of encoding, MPEG-2 compression encoding is used.

Hardware system composition

The voice recording device is shown in Figure 1. The entire system consists of ADC, DSP, CPLD controller, Flash large-capacity memory and LCD display screen.

Figure 1 System structure diagram

In this system, ADC is used to complete the conversion of the signal, the data format is selectable between 16, 18, and 20 bits. DSP is the core digital processor of the system. It is powerful and completes the compression coding of digital signals. CPLD is used for data Transmission control and initialization detection settings for devices such as ADC, Flash, and LCD display. Flash is used to store data, and LCD display is used to display the current system status, such as operation waiting and data processing. After the system is powered on, if there is a voice signal, enter the ADC, get a string of digital signals and send it to the DSP for data compression and encoding. The compressed and encoded data is stored in the Flash by the CPLD. The entire system works in a pipelined manner and collects data , Compression encoding and storage at the same time.

A / D converter UDA1341TS

UDA1341TS is a monolithic stereo A / D and D / A converter produced by Philips. It has an operating voltage of 3.0V, a signal-to-noise ratio of 97dB, a dual-channel input function, and a sampling frequency of 16, 32 and 44.1KHz Available.

UDA1341TS and DSP form a voice signal acquisition system, which mainly involves bit sampling clock (BCK), word synchronization clock (WS), sampling data output (DATAO), system clock input (SYSCLK), which have timing requirements. In the system, DATAO is used as an output pin and connected to the BDR0 pin of the DSP; BCK, WS, and SYSCLK are used as input pins, and their timing is supplied by the DSP. The system clock of UDA1341TS can only be 256Fs, 384Fs, 512Fs. The system clock can be selected and set by programming the SC0 and SC1 bits of the status register. Here Fs is the sampling frequency of the speech signal. When sampling data, WS is used to indicate the valid data output by DATAO of UDA1341TS. When the system samples the VINL (left channel) port, the rising edge of WS indicates the start of a frame of data, and the falling edge indicates the end of a frame of data; when the system samples the VINR (right channel) port, WS The falling edge of indicates the start of a frame of data, and the rising edge indicates the end of a frame of data.

UDA1341TS provides an L3 port, using the CPLD controller to program the L3DATA, L3MODE, and L3CLOCK pins of L3, and can set its internal registers. When the L3MODE pin is low, input register address information through the L3DATA pin; when the L3DATA pin is high, input data information about the register settings through the L3DATA pin (such as setting the chip system clock frequency, data input format, Chip working mode, etc.). UDA1341TS is connected to McBSP (multi-channel buffered synchronous serial port) of DSP. Various synchronization signals are generated by DSP, thus ensuring the normal reception of new data and the normal processing of received data. UDA1341TS and DSP hardware connection is shown in Figure 2.

Figure 2 UDA1341TS and DSP hardware connection diagram

Voice encoder TMS320VC5402

The compression of digital voice signals requires a large amount of digital signal processing, which is generally impossible for single-chip computers, so this system selects TI's DSP chip TMS320VC5402 (hereinafter referred to as C5402) to compress the voice signals.

C5402 communicates with UDA1341TS, a voice sampling converter, through its MsBSP. McBSP provides a full-duplex communication mechanism, as well as dual-buffered transmit registers and triple-buffered receive registers, allowing continuous data stream transmission, with data widths of 8, 12, 16, 20, 24, and 32 bits optional; The communication between McBSP and ADC is realized through the BDR0 pin, and the control of the communication process is realized by three pins such as BCLKR0, BCLKR1, and BFSR0.

CPLD low speed control

DSP as a high-speed arithmetic processor is not suitable for low-speed control applications. Detection, initialization of UDA1341TS, control of LCD and storage control of Flash are all low-speed controls. This system selects CPLD to accomplish these tasks. CPLD is Altera's EPM7128S, and the development simulation environment is Altera's MAX-PLUSII. Because the address lines A0, A1, and A2 of the DSP are to be used by some chips, a total of 6 address lines A3-A7 and A15 are selected and the inverse of the I / O space selection signal IS jointly generates the strobe signal of each chip in the system. The control circuit in CPLD is responsible for generating various read and write signals, such as Flash read signal MEM_RD and write signal MEM_WR.

In this system, C5402 should generate many control signals (such as the selection signal PPG2-PPGO of Flash program page, etc.), and also monitor and read the external status. Because the C5402 has only two general-purpose I / O pins, CPLD is used to expand the I / O port. An internal 8-bit DFF flip-flop is used to output data to the CPLD. In addition, through 8 tri-state gates, the 8-bit input state is placed on the lower 8 bits of the C5402 data bus. C5402 has 4 interrupt inputs INTR3 anti-INTR0 anti. The CPLD's interrupt selection module can select 4 of up to 8 external interrupt signals as C5402's interrupt input, which improves the flexibility of the system.

software design

Software design mainly includes the programming of ADC, the compression coding of voice data, etc.

ADC programming

The ADC samples at a sampling frequency of 16KHz and 16-bit quantization accuracy. The sampled bit synchronization signal, frame synchronization signal, and data bit clock signal are all provided by the DSP, so the programming of McBSP related registers, such as the pin control register (PCR) Programming, serial port controller (SPCR1, SPCR2) programming, receiving control register (RCR1x, RCR2x) and sending control register (XCR1, XCR2) programming will affect the final effect of the voice signal, so users must refer to the relevant information in detail before development .

Voice data encoding

In this paper, the general MPEG-2 speech compression coding algorithm is used. This algorithm is a frame data structure coding. The sample value of one frame is 576, which is calculated at the sampling frequency of 16KHz of UDA1341TS. The coding of one frame of data requires completion within 72ms. The instruction cycle of C5402 is 10ns. In the case of meeting the algorithm requirements, it takes about 10ms to perform dual-channel real-time encoding, so C5402 can complete the real-time encoding of the algorithm. It mainly includes the following aspects: operation of filter bank; operation of psychoacoustic model; quantization coding; formatting of frame data.

The role of the filter bank is to complete the mapping of the signal from the time domain to the frequency domain. The calculation of the psychoacoustic model is to use 1024-point FFT to analyze the input voice signal spectrum, and then combine the results of time-frequency mapping to calculate the masking characteristics of the human ears of each subband. Quantization coding is the process of calculating the bit allocation information required for each subband coding through the masking characteristics of the human ears of each subband and the output bit rate requirements, and linearly quantizing and coding each subband data. The follow-up work of the program is to format the data according to the MPEG-2 standard, and its purpose is to enable the data to be decoded correctly after encoding. The main program of the system is shown in Figure3.

Conclusion

After the system is powered on and run, it has been stable after many experiments. At present, the equipment has been commissioned and used on site, and part of the loading operation has begun, which meets the actual requirements of train voice recording.

Tag: TMS320VC5402 UDA1341TS