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Home > Other > Using EP1C3T144C6 chip and VHDL to realize the design of frequency mea

Using EP1C3T144C6 chip and VHDL to realize the design of frequency measuring meter

Published time: 2020-07-24 12:10:12

1 Introduction

In modern society, electricity resources have become an indispensable part of people's lives, and generators and motors play a very important role in the power system. In many cases, it is necessary to measure the frequency of the generator set and power grid. At present, there are many circuit systems for frequency measurement. Here is a digital circuit frequency measurement: FPGA-based frequency measurement meter for generator sets.

With the continuous development and progress of electronic technology, great changes have taken place in the digital circuit design represented by EDA. In terms of design methods, the traditional design method of "circuit design-hardware setup test-welding" has been changed to the electronic automation design mode of "functional design-software simulation-download and debugging". In this situation, a top-down electronic design method based on hardware description language and logic synthesis has been rapidly developed. The Verilog HDL language is currently the most widely used hardware description language. It is developed on the basis of the C language. Its grammar is relatively free and flexible, has a wide learning group, rich resources, and is easy to learn and understand. The design of the generator set frequency meter in this article is developed on the basis of Verilog hdl language. The source program has been synthesized and simulated (functional simulation and timing simulation) by Altera’s Quartus II 5.0 software, FPGA (Field Programmable Gate Array, on-site Programmable gate array) EP1C3T144C6 device of Cyclone series is selected.

2. Frequency measurement circuit

2.1 The overall circuit of frequency measurement

The voltage transformer is used to take the frequency measurement input signal from the terminal voltage of the generator set or the grid voltage, and after clipping and filtering, it becomes a stable waveform with basically the same amplitude. The signal is amplified and shaped by the amplifier circuit, and then compared with the voltage The circuit turns a square wave with positive and negative amplitude into a square wave signal with only positive amplitude. Then, the digital system of the FPGA is isolated from the input signal through an optocoupler. The FPGA digital system uses a standard 1HZ signal to count the number of pulses of the isolated square wave signal to obtain the frequency of the signal, which is displayed by the digital tube. Since the frequency of the generator set is related to the terminal voltage of the generator set, the change in the terminal voltage of the generator set can be obtained from the change in frequency. From the overall system block diagram shown in Figure 1, it can be seen that the FPGA digital system is isolated from the input channel, thus greatly improving the anti-interference ability of the system hardware.

Figure 1 Overall block diagram of the system

2.2 Principle of frequency measurement

The principle of frequency measurement is to count the number of pulses of the signal to be measured per second, that is, use a standard 1HZ (period of 1s) pulse width signal to count the pulses of the input signal to be measured, and collect the signal after the end of 1 second. The number of pulses is sent to the digital tube for display.

The frequency measurement controller has 3 input signals: Samplefreq is the standard pulse signal, Reset is the reset control signal, Start is the start measurement signal; 3 output signals: Endmeasure is the end measurement signal (count reset and conversion reset), Gate is allowed Count signal (ie, gate control signal), Enableconvert is the signal to start conversion. The control flow is to reset the frequency counter first, and then start the measurement. At the rising edge of the Samplefreq signal, the Gate signal enables the counter to start working. At the next rising edge of the Samplefreq, the Gate reverses to a low level to stop the counter from counting. Enableconvert makes the converter start to convert binary numbers (conversion time is less than 1s). After the conversion, the decimal number is decoded by a 7-segment display decoder, and then the frequency of the measured signal is displayed in the digital tube. Due to the use of the Enableconvert signal, the digital tube data display is stable without flickering. Before the next measurement, the frequency meter should be reset to clear the digital display of the nixie tube to prepare for the next display.

The digital cymometer designed in this paper consists of six modules: frequency measurement control module (Control), tenth frequency module (divfreq), binary counter module (Counter), latch module (Latch), binary to decimal converter module ( Bit2Bcd), 7-segment display decoder module (Led_encoder).

3. Design of frequency measuring meter

This design uses Verilog HDL language, using the top-down design concept. The system is divided into hierarchical functions according to functions. First, the top-level functional modules are defined, and the internal connection and external interface relationships of the top-level functional modules are described. The logical functions and specific implementation forms of the functional blocks are determined by the next-level modules. description. The whole design is divided into two steps: the first step uses Quartus Ⅱ5.0 graphics block input to design the top-level module, the top-level graphics block is shown in Figure 2; the second step is to generate a hardware description language (Verilog HDL) for each graphics block in the top-level module ), then in the generated Verilog HDL design file, the function of the low-level functional module is described and designed.

Figure 2 Top-level graphics block

3.1 Design of frequency measurement control module

This is a three-input three-output module. The waveform simulation of the frequency measurement control module is shown in Figure 3. For example, it is described in Verilog HDL as:

module Control (clk, reset, start, enableconvert, gate, endmeasure);

input reset, start, clk;

output enableconvert, gate, endmeasure;

reg enableconvert, gate, endmeasure;

always @ (posedge clk or posedge reset)


if (reset)


endmeasure enableconvert gate end



endmeasure if (start)


gate enableconvert end




Figure 3 The waveform simulation timing diagram of the frequency measurement controller

3.2 Module design of binary to decimal converter

In this design, the conversion clock Convertfreq signal is required to control the timing of the conversion module. Since the conversion is completed within 1s, the frequency of the conversion clock Convertfreq should be a high-frequency signal, that is, the frequency of the conversion clock Convertfreq is obtained by dividing the standard clock Samplefreq signal by 10 of.

In order to simulate the waveform of this design, take the input 10-bit binary number bin[9..0] as 10’b0000011001 (25 in decimal). Figure 4 shows the simulation timing diagram of the binary to decimal converter:

Figure 4 The simulation timing diagram of the binary to decimal converter

4. Simulation and debugging

Through the above description, the simulation is carried out from the independent perspective of each module, and the result shows that the design meets the requirements. In order to ensure the overall reliability of the system, the entire system is simulated.

Among them, LEDD, LEDC, LEDB, LEDA are the results of decoding to be displayed on the 7-segment digital tube, 0010010 (displayed as 2), 0100100 (displayed as 5).

Download the designed frequency meter to the target chip EP1C3T144C6, and perform the simulation on the GW48 experiment box. When a signal with a frequency of 1 Hz~1023 Hz is input, the frequency measured by the frequency meter is completely accurate. When the frequency is high At 1023 Hz, the system alarms and the frequency is displayed as 0.

5. Conclusion

Based on the FPGA-designed generator set frequency meter, the system adopts the isolation method of photoelectric coupler as a whole to improve the anti-interference ability and stability of the system. The system has the advantages of simple and reliable circuit, strong versatility and high stability, and can be widely used in frequency-voltage converters and speed relays.

The FPGA digital system part of this design uses Verilog HDL language, gives the core program, and can generate the corresponding hardware circuit through the Verilog HDL language synthesis tool, which has the superiority that the traditional logic design method can't compare. After simulation, it was verified that the design was successful and the expected result was achieved. At the same time, the digital electronic system designed by this method has strong portability and good changeability. If the required frequency measurement range needs to be expanded, there is no need to change the hardware, just change the software.



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