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Home > Other > The Ultimate Guide to Ring Counter: Working, Types & Applications

# The Ultimate Guide to Ring Counter: Working, Types & Applications

Update Time: 2023-08-28 15:26:18

## Contents

A ring counter can be envisioned as a circular arrangement of flip-flops organized in a shift register. This design ensures that the last flip-flop's output circles back to the starting point, creating a“circular”or“ring”pattern. Fundamentally, a counter's role is to tally pulses or events within a designated period. Flip-flops act as bi-stable devices, holding a singular binary figure (0 or 1), shifting their mode due to an incoming clock signal. Conversely, a shift register pools a series of flip-flops, each carrying distinct binary figures, and they advance one slot upon receiving each clock pulse.

## What is a Ring Counter?

A ring counter is a common application of the Shift register, closely resembling the shift counter. The key distinction lies in the connection of the last flip-flop's output to the first flip-flop's input in the ring counter, whereas in a shift register, it's channeled as output. Beyond this difference, all other aspects remain consistent.

The number of states in a Ring counter equals the number of flip-flops incorporated. So, to craft a 4-bit Ring Counter, one requires 4 flip-flops.

### Ring Counter Circuit Diagram

The diagram shows that the clock pulse (CLK) is disseminated to every flip-flop simultaneously. This design qualifies it as a Synchronous Counter. Additionally, each flip-flop is equipped with an Overriding input (ORI). The Preset (PR) and Clear (CLR) functions serve as the ORI. With PR at 0, the output reads as 1. Conversely, when CLR is set to 0, the output is 0. Both PR and CLR, active low signals, invariably operate at the 0 value.

With PR set to 0, the output Q becomes 1.

With CLR set to 0, the output Q turns 0.

These output states remain constant, irrespective of the input D's value or the Clock pulse (CLK). In operation, the ORI is linked to Preset (PR) in the first flip-flop, FF-0, and it's connected to Clear (CLR) in the subsequent flip-flops, FF-1, FF-2, and FF-3. As a result, the first flip-flop, FF-0, produces an output Q = 1, while the following flip-flops yield an output Q = 0. This unique output Q = 1 in FF-0 is referred to as Pre-set 1.

 ORI CLK Q0 Q1 Q2 Q3 low X 1 0 0 0 high low 0 1 0 0 high low 0 0 1 0 high low 0 0 0 1 high low 1 0 0 0

In the provided table, the emphasized 1's represent pre-set 1.

Pre-set 1 emerges when:

The ORI input is adjusted to a low value, at which point the Clk's state is inconsequential.

The ORI input is elevated to high, and a low clock pulse signal is introduced, corresponding to the negative clock edge activation.

A continuous loop is established as the pre-set 1 progresses to the subsequent flip-flop with each clock beat.

For a 4-bit counter, the following 4 states are attainable:

1 0 0 0

0 1 0 0

0 0 1 0

0 0 0 1

### What is 8 bit Ring Counter?

An 8-bit ring counter can be constructed using eight D latches linked sequentially, with the final latch's output directed back as the input for the initial latch. The output from the first activated latch, Q1, is fed into the second activated latch, and the pattern continues. A clock pulse generator circuit produces clock pulses for this arrangement.

## Working of Ring Counter

Imagine a situation where the pre-set configuration reads '0000'. Under this setup, for FF0, the output indicated at Q0 is '1'. However, for the subsequent units like ff1, ff2, and ff3, all tied to the 'clear' function (with CLR being 0), the Q1, Q2, and Q3 readings consistently show '0'. This pattern is consistent with the truth table's details, and the corresponding waveforms can be visualized when processed through the Verilog HDL code in the Xilinx program.

### Ring Counter Truth Table

 ORI CLK Q0 Q1 Q2 Q3 Low Pluse X 1 0 0 0 1 0 0 1 0 0 1 0 0 0 1 0 1 0 0 0 0 1 1 0 1 0 0 0

Where,

Inputs encompass ORI and CLK.

X signifies that the Clock can transition via a positive or negative edge.

Outputs are labeled as Q0, Q1, Q2, and Q3.

Analyzing the table, it's evident that the value '1' progresses diagonally from Q0 through to Q3 and subsequently circles back to 'Q0'. This behavior underlines its operation akin to a ring counter.

## Verilog HDL Program for Ring Counter

module dff(q,d,c);

output q;

input d,c;

reg q;

initial

q=1’b1;

always @ (posedge c)

q=d;

end module

module dff1(q,d,clk);

output q;

input d,clk;

reg q;

initial

q=1’b0;

always @ (posedge clk)

q=d;

endmodule

module ring(q,clk);

inout [3:0]q;

input clk;

dff u1(q[0],q[3],clk);

dff1 u2(q[1],q[0],clk);

dff1 u3(q[2],q[1],clk);

dff1 u4(q[3],q[2],clk);

end module

### Timing Diagram of Ring Counter

Below, you'll find the timing diagram representative of the ring counter.

## Types of Ring Counter

There are two types of Ring Counter.

### Straight Ring Counter

This is often referred to as the One Hot Counter. Within this design, the output from the concluding flip-flop links directly to the input of the initial one. The primary characteristic of this Counter is its ability to cycle a solitary one (or zero) bit throughout the loop. In this setup, the first flip-flop employs Preset (PR), while the subsequent three flip-flops utilize the Clock (CLK).

### Twisted Ring Counter

This is alternatively termed a switch-tail ring counter, strolling ring counter, or a Johnson counter. It links the inverse of the last shift register's output to the input of the premier register, allowing a sequence of ones to be trailed by zeros circularly.

In this configuration, every flip-flop is governed by the Clock (CLK). For the Twisted Ring Counter, the total states equal twice the count of flip-flops involved.

## Difference between Ring Counter and Johnson Counter

Below is a comparison between the ring counter and the Johnson counter.

 Ring Counter Johnson Counter The final flip-flop's output is channeled into the initial flip flop's input. The concluding flip-flop's output is inverted and provided to the beginning flip flop as input. The count of states equals the number of flip-flops employed. When utilizing 'n' flip-flops, '2n' states are necessitated. Input frequency = n Input frequency = f Output frequency = f/n Output frequency = f/2n Total unused states = ( 2n – n) Total unused states = ( 2n – 2n)

Ring counters offer certain advantages and disadvantages when contrasted with other counters.

• There's no requirement for a decoder, meaning it's a self-decoding setup. It possesses the capability to both encode and decode logic.

• It's feasible to create using both JK and D flip-flops.

• Within the ring counter, 4 out of the 15 potential states are in use.

• It isn't self-initiating.

## Applications of Ring Counter

Ring counters have various uses like Frequency counters, ADC, Digital clocks, and measure timers and rates. Here are the applications:

• In hardware crafting, especially with ASIC and FPGA designs, ring counters are pivotal in establishing finite-state machines that oversee sequential logic setups.

• They are instrumental in producing timing markers for synchronous entities, encompassing clocks, timing devices, and frequency partitioners.

• Ring counters facilitate construction of circular storage or queues in memory components such as RAMs or FIFOs.

• For encryption or evaluation tasks, ring counters come in handy to formulate pseudo-random figures or series.

• Ring counters help design revolving visual displays or LED pursuit lights for ornamental or alert functions.

## Conclusion

A ring counter operates as a shift register counter with a looped design, achieved by linking the last flip-flop's output directly to the input of the initial one. Two primary variations exist: the straight ring counter and the twisted ring counter. Each boasts distinct characteristics with their respective pros and cons. These counters find their utility in hardware architecture and digital frameworks.

## FAQ

• What is a SISO shift register?
• "SISO" delineates "Serial-In, Serial-Out". In such a configuration, data is ingested sequentially at its entrance and methodically emitted from its exit. The clock signal rate dictates the progression of bits before the introduction of the succeeding one. This kind of shift register is adept at acting as a liaison between two non-synchronous gadgets, allowing them to interface despite signal rhythms or interval disparities.

• What is the difference between ring counter and shift register?
• A ring counter is designed as a shift register that forms a circular pattern. The entry at the commencement of this cycle is influenced by logical associations stemming from multiple locations inside the register.

• How does a 4-bit twisted ring counter work?
• When Q0 is channeled to the serial input, the ensuing configuration is labeled as a twisted ring or Johnson Counter.

• What is the modulus of 3-bit ring counter?
• The 3-bit Johnson counter has a MOD of 6. Consequently, it presents 6 distinct state numbers.

• How many states are there in the 10-bit ring counter?
• In the 10-bit ring counter, 10 states are employed.

• What is Johnson counter?
• The Johnson Ring Counter, also known as the "Twisted Ring Counter," mirrors the regular Ring Counter's feedback structure. The distinction lies in connecting the last flip-flop's inverted output Q back to the first flip-flop's input D.

• What is a ring counter same as?
• It is the same as the shift counter.

• What is the difference between straight and twisted ring counter?
• For the straight ring counter, the result from the concluding flip-flop is channeled to the input of the initial one. Meanwhile, in the twisted ring counter, every flip flop takes the ORI input as its reset instruction.

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