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Home > Processor/DSP > The design of intelligent instrument based on DSP device TMS320C32 and

The design of intelligent instrument based on DSP device TMS320C32 and CPLD chip

Published time: 2020-08-11 16:45:15

1. Background and superiority of DSP+CPLD system

As the main electrical equipment, the electric motor is the most numerous one. The normal operation of the electric motor and its protection is directly related to the national economy and people's livelihood. According to statistics, reliable protection can reduce the burning of more than 200,000 units (times) of motors each year, reducing economic losses by hundreds of millions of yuan.

Most of the traditional intelligent instruments are developed on the basis of the single-chip microcomputer system. The protection device based on the single-chip microcomputer is restricted by its internal structure, clock and bus, with weak computing power, poor real-time performance, weak software and hardware versatility, low system flexibility, and increasingly unable to meet the above needs. The DSP processor uses a Harvard structure that is different from the traditional single-chip von Neumann structure, which overcomes the bottleneck effect of the transmission channel caused by the fetching of instructions and data through the same bus. Programmable logic devices (PLD) have evolved from low-density PLDs such as PROM, PLA, PAL, and GAL to two large-scale PLDs, CPLD and FPGA. Development tools have become more and more complete and applications have become more and more popular. Combining CPLD/FPGA and DSP technology to realize a DSP device system solution provides sufficient practical feasibility for the development of measurement and control instruments in the direction of high-level intelligence.

In order to realize the intelligent on-line monitoring of large-scale equipment in the power system, this article takes the WSM2000 DSP intelligent motor protection device project as the background to research and design a new type of DSP+CPLD intelligent instrument structure.

2. System structure

This system uses the floating-point DSP device TMS320C32PCM60  produced by American TI company as the main processing device at the bottom to realize the processing of the digital signal acquired by A/D, and design all control circuits and address allocation in EPM7128S to make the whole system structure Simplification, miniaturization, and diversified functions. AD1674 is used for signal acquisition, and FLASH Memory is used to store software codes, main functional parameters, fault data records, etc.; the function of SRAM is one for program simulation, and the other is to use the software in FLASH Memory when the system is running offline. Transported to SRAM to run, improve the efficiency of soft operation. The system function module is shown in Figure 1.

System function module diagram.png

3. CPLD development process

The development of CPLD refers to the whole process of using the CPLD chip and with the aid of its development system, according to the working steps of the development system, converting the user design into CPLD configuration data and downloading it to the CPLD chip to realize the user design requirements. Its design flow chart is shown as in Fig. 2.

CPLD development flow chart.png

4. liquid crystal display (LCD) module design

1 Hardware interface design Built-in T6963C controller type LCD module interface

Which is composed of instruction latch, data latch, data buffer, status register, data control circuit, data stack area, etc. The interface unit realizes the access operation of the CPU and the internal registers of the T6963C and the display memory managed by it, and realizes the conversion between the CPU operation timing and the internal working timing of the T6963C. Each time the CPU operates T6963C, the latch of the interface section retains the instruction code or display data sent by it, and immediately blocks the external circuit of the interface section, and transfers the subsequent processing process to the working sequence of the T6963C control section. On the other hand, until the processing is completed, the external circuit of the interface part will be released and wait for the next access. The interface between T6963C and TMS320C32 and EPM7128S is shown in Figure 3:

The /IOSTROB, A1, A0 and pins of TMS320C32 perform address decoding and participate in the unified addressing of the system. /IOSTROB=0, the corresponding effective address of DSP is 810000H--82FFFFH, when the address line A0 is 1, the LCD is strobed, the address line A1 is used to distinguish the data channel and the instruction channel of the liquid crystal, and when A1=1, it is the instruction channel , When A1=0, it is the data channel. The LCD interface address is: 818003H is the command channel and 818001H is the data channel.

Figure 3 Hardware interface diagram.png

2 software design

The T6963C interface part of this system has designed a data stack. When writing instructions with parameters, the parameters are written to the data channel first, and the interface part stores them in the data stack, and then the channel writes the instruction code. T6963C will process the latest data in the data stack as its parameters according to the meaning of the instruction code. When reading display data, first write the instruction code of the operation, T6963C puts the required display data into the data stack, and then read data operation to read the data in the data stack.

3 Software realization of built-in T6963C LCD module

(1), address allocation and definition

.data

LCDC_ADD .equ 820003H; instruction channel

LCDD_ADD .equ 820001H; data channel

(2) Status word detection subroutine

LCDR_ST: LDI @LCDC_ADD, R0

RETS

This program derives a subroutine to determine the relevant flag:

"1" The subroutine for judging the status bits STA1 and STA0, these two flag bits must be "1" at the same time before the read and write data of the write command.

LCDST01: CALL LCDR_ST

LDI R0, R1

AND 01H, R1

BZ LCDST01

AND 02H, R0

BZ LCDST01

RETS

"2" Judgment status bit STA3 subroutine (data automatic writing status)

LCDST3: CALL LCDR_ST

AND 08H, R0

BZ LCDST3

RETS

(3), write instructions and write data subroutine

LCDPR1: CALL LCDST01; double-byte parameter command write entry

LDI AR1, R0

CALL LCDPR13

LCDPR11: CALL LCDST01; single-byte parameter command write entry

LDI AR2, R0

CALL LCDPR13

LCDPR12: CALL LCDST01; no parameter command write entry

LDI AR3, R0

LCDPR14: STI R0, @LCDC_ADD; write instruction operation

RETS

LCDPR13: STI R0, @LCDD_ADD; write data operation

RETS

(4) Subroutine for reading data

LCDPR2: CALL LCDST01; judgment status bit

LDI @LCDD_ADD, R0; read data operation

RETS

5. System online programming

Because the system will eventually run independently from the emulator, the program must be programmed into the non-lost memory FLASHROM after power failure. The method of installing the memory on the user circuit board for programming used in the development of this system loads the user program code into the FLASH memory. It includes the commonly used In System Programming (ISP), which realizes the programming of FLASH memory through the microprocessor of the system.

1. FLASH online programming realization

The basic operations of FLASH mainly include read, byte programming, reset, sector erase, chip erase, etc. Am29F010B flash memory read operation is the same as ordinary memory operation, no specific time sequence is required. After the circuit is powered on or internal programming and other operation techniques, it automatically enters the read data state. The erase and write operations are relatively complicated. It cannot simply write directly, the .OUT file cannot be loaded into FLASH, and the LOAD commands in CCS and C Source Debugger cannot write to FLASH. A special program is required to write a series of Flash Memory command registers, and then call the embedded The internal program of the formula algorithm completes the corresponding command. The general steps of Am29F010B programming are reset, erase, byte programming and so on.

2. System software loading program design

The main function of the system software loader is to load a piece of code that starts to execute after the system is powered on and the processor is initialized. It loads the user's real-time running program and data from the external low-speed FLASH Memory to the internal or external high-speed static RAM memory, and then jumps At the entry point of the program, it starts running at full speed.

TMS320C32 DSP chip boot loader execution process will reset the start address of the boot program stored in the interrupt vector table. After power-on reset or manual reset, the program pointer will point to the boot program. Before running the move program, pay attention to the shutdown interrupt. If MC/MP#=1 and the system is not connected to the emulator, the DSP chip will automatically run the boot loader solidified in 0h~0fffh. This program will automatically determine whether it is INT0~INT2 or INT3 interrupt. If it is INT0~INT2 interrupt, DSP will load a section of program stored in BOOT1~BOOT3 into on-chip RAM or off-chip SRAM; if it is INT3 interrupt, DSP will load the program from serial port to on-chip RAM or SRAM . If there is no interruption, the DSP jumps to the unit indicated by the vector as the first address according to the reset vector in the 0H unit, and executes a boot loader. The key codes of TMS320C32 boot loader are as follows:

LDI 01H, AR0

LDI *AR0, AR0

LDI 02H, AR2

LDI *AR2, AR1

LDI 87, RC

RPTB dload

LDI *AR0++, R0

Dload: STI R0, *AR1++

LDI 03H, AR0

LDI *AR0, AR0

LDI 04H, AR2

LDI *AR2, AR1

LDI 4000H, RC

RPTB pload

LDI *AR0++, R0

Pload: STI R0, *AR1++

BR 900000H

6. Concluding remarks

The methods discussed above have been implemented in both software and hardware, with ideal results. Utilizes the embedded algorithm of Flash ROM, embodies the high efficiency and flexibility of DSP. It is very suitable for real-time control system, which solves the problem of only relying on the burner, and can also adjust the system parameters frequently, which reduces the system cost and shortens the system development cycle.


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