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Home > RF/Wireless > Novel ASIC Helps Sources Silence Noise

Novel ASIC Helps Sources Silence Noise

Update Time: 2019-12-20 00:00:00

Novel ASIC Helps Sources Silence Noise

Phase noise is a critical performance parameter in many applications—from communications to radar systems, and from commercial to military uses—and techniques that generate RF/microwave signals while minimizing phase noise are always of interest.

Synergy Microwave Corp. has long been associated with low-noise RF/microwave signal sources and novel techniques for signal generation. The firm has now developed a phase-locked synthesizer and fixed-frequency, phase-locked-oscillator (PLO) design that can be applied to the generation of low-noise fundamental-frequency signal sources from 100 MHz to 15 GHz—and extendable to 30 GHz , when using an external frequency doubler from Synergy. Even more remarkable, these quiet signal sources fit within compact industry-standard 2.25 × 2.25-in. module housings, or on a 1.0 × 1.25 in. surface-mount-technology (SMT) footprint.

The low-noise PLO/synthesizer connectorized module version (Fig. 1) and surface-mount version build upon a unique state-of-the-art phase-lock-loop (PLL) application-specific-integrated-circuit (ASIC) device—one that enables extremely high frequency range and versatile divider/phase-detector flexibility for phase-locking RF and microwave signal sources. These include dielectric-resonator oscillators (DROs) and various-topology voltage-controlled oscillators (VCOs). The proprietary ASIC makes it possible to phase lock these and other wide-band, high-frequency oscillators with bandwidths beyond octave tuning.

These synthesizers or fixed LO sources can lock to almost any reference source even through microwave frequencies, such as stable crystal oscillators and multiples thereof, and can function effectively in a number of different operating modes. The ASIC makes an excellent, low-noise starting point for such component functions as high-frequency dividers and phase detectors, as well as phase-locked fixed-frequency and tunable frequency sources.

The PLL design supports both single- and dual-loop modes of operation with a wide array of reference sources. In single-loop mode of operation, for example, it can work with reference frequencies from 1 MHz to as high as 2.2 GHz, enabling the addition of a synthesized single-loop frequency source to a wide range of systems. In dual-loop mode of operation, the PLL ASIC can lock a first-loop reference crystal/frequency-multiplier combination to supply an output, second-loop PLL a reference frequency signal up to 1 GHz.

The ASIC enables particularly low single-sideband (SSB) phase noise from both the single- and dual-loop source configurations with the industry-leading lowest noise digital divider and phase detector. Measurements taken with a model FSUP signal source analyzer from Rohde & Schwarz for a 10-GHz dual-loop synthesizer at 10 GHz show the excellent loop noise performance and sharp drop in phase noise further from the carrier using a low-noise voltage-tuned DRO from Synergy (Fig. 2).

A frequency-synthesizer PLO module with this ASIC can be used to construct dual-loop phase-locked DROs to 14.5 GHz as well as dual-loop frequency synthesizers in octave bands to 10 GHz, these latter sources with frequency settling times of less than 100 μs. Either of these dual-loop configurations can also accommodate virtually any reference frequency. Dual-loop capability also offers the benefit of reference cleanup of unwanted spurious signal products and noise that may exist on a necessary reference time standard.

The initial primary loop’s narrow bandwidth and excellent crystal or surface-acoustic-wave (SAW) oscillator noise performance—coupled with the lowest available digital phase detector noise floor—yields performance only previously seen using analog samplers or fundamental mixer/phase-detector techniques. Fixed and Frequency Agile models are both available with dual output or coupled sample output. Modules can also be configured to output a reference or internal first loop sample.

Both connectorized single KSLSO and dual-loop KDSLO versions communicate using a simple channel-select SPI connection. Custom program interfaces are also available to suit specific interface applications. It is only necessary to communicate with one channel-select register. 


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