Microchip Enters Memory Infrastructure Market Pushes Industry's First Commercial Serial Memory Controller
Published time: 2019-12-20 10:53:35
The SMC 1000 8 x 25G supports the high memory bandwidth required for next-generation CPUs and SoCs for artificial intelligence and machine learning.
As the computational demands required for artificial intelligence (AI) and machine learning workloads continue to increase, traditional parallel-connected DRAM memories have become a major obstacle to next-generation CPUs due to the need for more memory channels to provide more memory bandwidth. Microchip Technology Inc. today announced the entry into the memory infrastructure market with the industry's first commercial serial memory controller to expand its data center portfolio. The SMC 1000 8 x 25G enables CPUs and other compute-centric SoCs to use four times the memory channel of parallel DDR4 DRAM in the same package size. Microchip's serial memory controllers not only provide higher memory bandwidth and media independence for compute-intensive platforms, but also feature ultra-low latency.
As the number of CPU processing cores increases, the average memory bandwidth available to each processing core is limited by the fact that CPUs and SoC devices cannot scale the number of parallel DDR interfaces on a single chip to meet the ever-increasing number of cores. decline. The SMC 1000 8 x 25G is connected to the CPU via a 25 Gbps channel that conforms to the 8-bit Open Memory Interface (OMI) and is connected to the memory via a 72-bit DDR4 3200 interface, dramatically reducing the host CPU or SoC required for each DDR4 memory channel. The number of pins allows for more memory channels and increases the available memory bandwidth.
OMI-capable CPUs or SoCs can use a large number of media types with different cost, power, and performance metrics without the need to integrate separate memory controllers for each type. In contrast, current CPU and SoC memory interfaces are typically locked at a specific interface rate to a particular DDR interface protocol, such as DDR4. The SMC 1000 8 x 25G is the first memory infrastructure product in the Microchip product family to support a media independent OMI interface.
Data center application workloads require OMI-based DDIMM memory products to provide the same high performance bandwidth and low latency effects as today's parallel DDR-based memory products. Microchip's SMC 1000 8 x 25G features an innovative low-latency design with less than 4 ns delay compared to traditional LRDIMM-based integrated DDR controllers, indicating bandwidth and time for OMI-based DDIMM products. The performance is almost the same as similar LRDIMM products.
Pete Hazen, vice president of data center solutions business at Microchip, said: "Microchip is pleased to introduce the industry's first serial memory controller product to the market. New memory interface technologies, such as the Open Memory Interface (OMI), enable a large number of SoC applications. Ability to support the growing storage needs of high-performance data center applications. Microchip's entry into the memory infrastructure market underscores our commitment to improving data center performance and efficiency."
Steve Fields, chief architect of IBM Power Systems, said: "The workload of IBM customers' workloads has soared. Therefore, we made a strategic decision on the POWER processor memory interface and decided to use the OMI standard interface to increase memory bandwidth. Happy to partner with Microchip to launch the solution."
SMART Modular, Micron and Samsung Electronics are developing multi-pin, high-efficiency 84-pin differential dual in-line memory modules (DDIMMs) ranging in size from 16 GB to 256 GB in JDEC DDR5 draft DDIMM packages. These DDIMMs will feature the SMC 1000 8 x 25G and will seamlessly interface to any OMI-compliant 25 Gbps interface.
OpenCAPI Alliance Chairman Myron Slota said: "The Open Memory Interface (OMI) standard provides a high pin efficiency serial memory interface, so a large number of CPU and SoC applications can expand memory bandwidth and are emerging more and more Seamless transition between media types (such as storage staging memory). The OpenCAPI Alliance provides host and target IP for free, and will initiate a series of measures at the same time to ensure compliance."
Rob Sprinkle, head of infrastructure technology at Google LLC platform, said: "Google customers can benefit from data-intensive applications such as machine learning and data analysis that require high-performance storage. Google strongly supports open standards-based initiatives such as open memory interfaces. (OMI), they provide a high-performance memory interface to meet important performance goals such as bandwidth and latency."
To support customers developing OMI-compliant systems, the SMC 1000 is equipped with design software and ChipLink diagnostic tools to provide a range of debugging, diagnostic, configuration and analysis tools through an intuitive GUI.
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