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Home > Programmable logic > integrate FPGAs: embedded FPGAs (SoC) and FPGA Chiplets (SiP)

integrate FPGAs: embedded FPGAs (SoC) and FPGA Chiplets (SiP)

Update Time: 2021-06-15 11:29:24

FPGAs are widely popular in systems for their flexibility and adaptability. It is increasingly being used in high-volume applications. As volumes grow, system designers may consider integrating FPGAs into SoCs to reduce cost, lower power and/or improve performance.


There are two options for integrating FPGAs into SoCs: o FPGA chiplets, which replace power-hungry SERDES/PHYs with special die-to-die interconnects that communicate with the companion SoC die o eFPGAs, which are a block of IP placed on the SoC die, How do these options compare? As we will see, it depends on the application and the priority.


In some applications, integrated FPGAs offer advantages: 

   1.Pairing FPGAs with SoCs in existing systems, such as smart NICs or Microsoft Azure

   2. Providing flexibility for SoCs to change algorithms and/or protocols as standards change or as different customers demand

   3. Accelerating SoCs, with critical workloads running faster than processors on parallel FPGAs.

   4. Providing flexibility for architectures with programmable state machines for architectures with arrays of computational elements, such as many of the new AI gas pedals


eFPGA (SoC and cFPGA (SiP)

The two popular integration schemes are embedded FPGA (hereafter referred to as eFPGA integration scheme) and FPGA Chiplets (hereafter referred to as cFPGA integration scheme) 1. eFPGA integration scheme eFPGA is an FPGA IP core embedded in a SoC, either soft or hard core, and the process node often needs to be aligned with the SoC to be consistent with the SoC.

Embedded FPGA.png

                                                                                                           Framework of eFPGA

Embedded FPGA-2.png

                                                                                                              The eFPGA Concept


eFPGAs typically have more inputs and outputs than traditional FPGAs, and can be connected to buses, data paths, control paths, PHYs, and other components. This technology was proposed in academia many years ago, and only in the last 5 years has it gradually become widely accepted. A series of companies focused on eFPGAs have emerged in the US, France, and China, and have successfully commercialized them. cFPGA integration solution Chiplet, on the other hand, was first conceived from DARPA's CHIPS (Common Heterogeneous Integration and IP Reuse Strategies) project. It is by way of die-. to die internal interconnect technology to package multiple modular chips with the underlying base chip to form a multifunctional heterogeneous system. Package (SiP) chip model. Theoretically, this technology is a short-cycle, low-cost integration of third-party chips (e.g., I/O, memory chips, NPUs, etc.) where the process nodes of individual module chips can vary. chiplets are one of several industry efforts to compensate for the slowing growth of silicon process technology. They originated as multi-chip modules and were born in the 1970s. To date, a number of companies have created their own Chiplet ecosystems early on, including Marvell, AMD, Intel, and others.

Embedded FPGA-3.png

                                                                                                                                Chiplet's Framework

Embedded FPGA-4.png

                                                                                                                           Chiplet concept

Power hungry high speed SERDES are the connecting tiles in this diagram. EMIB is Intel's proprietary wide bus high bandwidth chip-to-chip interconnect. The FPGA chips in between are primarily digital logic. Intel and Ceres will provide chips for at least some customers to integrate into the SoC using a plug-in connector, see example below.   

Embedded FPGA-5.png

Intel interchip interconnect technology solution (from Intel) In this way, a SoC and an FPGA chip can be co-packaged, connecting them with a wide high-speed bus. The latest FPGAs (both X and I) actually use Chiplet technology, and Intel has given its own inter-chip interconnect technology a lofty name: "Embedded Multi- die Interconnect Bridge". Xilinx has been using inter-die interconnect technology since the 7 series to achieve the convergence of large logic capacity, Serdes high-speed interfaces, and HBM high-bandwidth storage in a limited area through stacking.

 Embedded FPGA-6.png

                                                                                             History of Xilinx inter-chip interconnect technology

Pros and cons of cFPGA vs eFPGA

Comparison of the advantages and disadvantages of the two solutions

The disadvantages of the chip approach are: o High cost of multi-chip packaging using substrates o Requires a dedicated chip-to-chip interface on the SoC, which you may not be familiar with or able to obtain from PHY IP vendors o The smallest FPGA chip still has a large number of LUTs that may exceed requirements. o The die cost of eFPGA+SoC is lower than the cost of the inlier and chip+SoCo. Such small chips are not available and the required chip area on the SoC is minimal o The architecture has eFPGAs distributed in many locations on the chip, e.g. in an array of compute elements. eFPGAs are a programmable state machine for local control of high-speed compute blocks: small chips are actually only available for a single large block of FPGAs.


Advantages of the cFPGA SiP solution.

1. Supports inter-chip fusion of multiple process nodes.

2. Designed to create standardized, modular IP, so the FPGA part is usually a fixed-chip module and SiP designs are faster to reconfigure and iterate.


Advantages of eFPGA SoC solutions.

1. No need to go through SoC inter-chip interconnect technologies that you may not be familiar with (sometimes not available from your PHY IP provider).

2. Eliminate the need for costly multi-chip package substrates.

3. Designed to enhance the customizability of FPGAs and be more flexible in terms of individual details customization.


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