How Intel AGILEX FPGAs are compatible with CXL
Published time: 2019-12-20 10:35:06
Since Intel acquired Altera for $16.7 billion a few years ago, the introduction of the FPGA portfolio has been largely a product of the pre-Intel era. However, for a long time, there was no strong product launch, which caused Altera's original market to be eroded by major competitors such as Xilinx. However, in the past few years, Intel has not been idle, but spent time and energy on integration with Altera's internal technology.
On the day of 2019.4.2, Intel announced its first completely independently designed FPGA, based on its internal 10nm process, using the new Agilex designation. This new line of products will be sampling later this year and will offer a mix of analog, digital, memory, custom IO and eASIC variants on a single platform.
Many of the innovations included in the new Intel Agilex FPGA devices include a high-bandwidth, low-latency, computational fast link (CXL) coherent processor interface IP. Intel spent four years developing the CXL specification. In March of this year, Intel joined eight other founding members - Alibaba Group, Cisco, Dell EMC, Facebook, Google, Hewlett-Packard Enterprise (HPE), Huawei and Microsoft, and announced the establishment. A consortium to jointly develop CXL as an open interconnect technology for accelerated computing, using software-driven CPUs and specialized hardware accelerators to accelerate compute-intensive workloads.
CXL is also an open source protocol standard that provides high-performance connectivity between one or more host processors and other subsystems or devices, including accelerators, memory buffers, and intelligent I/O devices. Based on the PCI Express (PCIe) 5.0 physical layer infrastructure, CXL is designed to address the proliferation of high-performance computing workloads through heterogeneous processing and memory systems. Artificial intelligence and machine learning (AI/ML), communications and networking systems, and high-performance computing (HPC) applications benefit from CXL's consistency and memory-enhancing performance.
The CXL interconnect protocol runs on top of the PCIe 5.0 PHY, using x16, x8, and x4 link bandwidth. CXL 1.0 debuted at a transfer rate of 32 GT/s, which means a transfer rate of 64 GB/s in each direction. The CXL standard supports standard PCIe devices and CXL devices on the same link.
Leveraging the PCIe 5.0 infrastructure makes it easier for devices and platforms to adopt the CXL standard without having to design and validate new high-speed physical layers, describe new channels, or develop new channel expansion devices such as retimers.
The CXL standard consists of three protocols:
The CXL IO protocol is based on the existing PCIe protocol and uses standard PCIe features including device discovery, configuration, initialization, I/O virtualization, and direct memory access (DMA).
The CXL Cache Protocol uses a simple response protocol that allows connected devices to cache data obtained from host CPU memory. The host processor uses cache-snoop messages to manage the consistency of data at the device level cache.
The CXL memory protocol allows the host processor to directly access memory attached to other CXL devices in a cache-consistent manner. CXL memory transactions consist of simple load/store.
While CXL IO can reuse most of the PCIe software infrastructure with existing device drivers and system software, drivers and software will inevitably need to be enhanced to take advantage of CXL cache and CXL memory capabilities.
It should be noted that Intel has also enhanced Agilex FGPA's capabilities in artificial intelligence to support enhanced support provided by Bfloat16/FP16, INT7/INT2, and even other low-precision digital formats. Combined with an internal configurable DSP, AI performance of up to 40T FLOPS can be achieved. In addition, under the management of the Intel OneAPI strategy, Agilex FGPA works with Intel's CPU, Nervana, and Movidius' Myriad series of VPUs.
Intel currently offers three versions of the Agilex FGPA portfolio: the F, I, and M series. The Intel Quartus Prime software will support the new series starting this month, but the F series will not be available until the third quarter of this year.
What is Intel's newly formed CXL organization?
A consortium of technology companies has formed a new standard called Compute Express Link to provide ultra-fast interconnection between the data center central processing unit (CPU) and the accelerator chip.
The goal is to provide breakthrough data center performance that helps computers keep up with the explosive growth of Internet of Things (IoT) data.
Navin Shenoy, executive vice president and general manager of Intel Data Center Group, said in a blog post that CXL will eliminate bottlenecks between CPU and data center-specific accelerator chips. This is an example of how Intel not only sees itself as a CPU company, but also the shepherd of the entire PC and server business. As the company said in its recent construction day event, its focus is on processing, architecture, memory, software, security and interconnects.
The new Compute Express Link (CXL) will accelerate fast-growing data workloads such as artificial intelligence and machine learning, rich media services, high-performance computing and cloud applications.
"CXL is an important milestone in data-centric computing and will be the foundation for an open, dynamic accelerator ecosystem," said Jim Pappas, director of Intel's technology program, in a statement. "Like Intel and the PCI Express, we can look forward to a new round of industry innovation and customer value through the CXL standard."
CXL Specification 1.0
The team has approved CXL Specification 1.0, which will improve communication between the CPU and other devices such as secondary processors or accelerators. It will provide improved interconnect and better memory consistency for higher performance in data-intensive applications.
The new open standards will help create an open accelerator ecosystem for high-performance, heterogeneous computing, encouraging interested member companies and institutions to join. It is worth noting that Intel's competitor Advanced Micro Devices has not yet become part of the consortium. CXL is an open industry standard designed to support data center accelerators and other high-speed, enhanced open ecosystems. The 1.0 specification is available now.
"CXL is a direct competitor to CCIX and IBM's OpenCAPI and Nvidea's NVLink," said Tirias Research analyst Kevin Krewell. "This is Intel's alternative to CCIX. Both CXL and CCIX use PCIe as the underlying electrical connection. Unfortunately, there are two directly competing standards trying to do the same thing - connecting CPUs and accelerators (like neural network chips, GPUs and FPGAs) In a memory coherent protocol (PCIe is not a coherent interface).
The dispute over the agreement, Intel chose to be a self-contained
Standard organizations similar to CXL include CCIX, OpenCAPI, and Gen-Z Consortium (Gen-Z). These standards organizations have also been established as early as 2016. CCIX and CXL are both under the PCIe standard for the underlying connection protocol. As far as the existing members of each agreement are concerned, AMD, IBM, Xilinx, and Huawei all participate in the agreements. NVIDIA also has its own NVLink. Intel is the main player of the server CPU, but it has not been in the initial list of relevant standard agreements. Column, even the OpenCAPI Alliance has said that Intel is welcome to join.
After three years, Intel did not join the existing standard organization, but chose to pull Microsoft, Ali, Cisco, Dell EMC, Facebook, Google, HP, Huawei eight giant companies to form the CXL alliance. Nacin Shenoy, executive vice president and general manager of Intel Data Center Group, said in his blog post that "although there are other interconnection protocols, CXL is providing CPU/device memory consistency, reducing device complexity, and integrating the industry in a single technology. The standard physical and electrical interfaces are unique."Tag: Intel
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