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Home > Programmable logic > FPGA development full Raiders - debugging

FPGA development full Raiders - debugging

Published time: 2019-11-06

Debugging experience in large-scale design

Debugging on a large scale should be done in the reverse order of the design philosophy, starting from the ground up and relying on the ChipScope Pro tool.The following mainly introduces the use of ChipScope Pro and FPGA Editor components.

ChipScope Pro component application example

In syringes software design tools, ISE integrates all syringes tools and programs.ChipScope Pro is no exception, and the ISE treats it as a class of source files on par with HDL source files, IP Core, and embedded systems.This section implements a counter module on the Xilinx spartan3e-d development board, which explains how to create ChipScope applications in ISE and how to observe and analyze data.

Example 5.6.1: implement an 8-bit counter in ISE and use ChipScope to analyze its logical output.

(1) create a new user project and add the source file of mycounter. V, the contents of which are listed as follows:

The module mycounter (CLK, reset, dout);

The input CLK.

Input the reset;

The output [away] dout;

Reg [away] dout;

Always @ (posedge CLK) begin

If (reset = = 0)

Dout < = 0;

The else

Dout <= dout + 1;

The end

endmodule

Then according to the circuit connection, add the corresponding pin constraints.

(2) comprehensive project, and then from ISE project management area, right click, select the "Add New Source" command, select the "ChipScope Definition and Connection File" type in the pop-up dialog box, and enter the ChipScope design Name mychipscope in the "File Name" column, as shown in figure 5-41.

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Figure 5-41 schematic diagram of adding ChipScope design

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Figure 5-42 test module selection interface

Click the "Next" button to enter the selection interface of analysis files, where all HDL designs and schematic designs in the folder will be listed (including the top module and all the bottom modules) for the user to select, which can be selected with a single mouse click. In this example, select mycounter, as shown in figure 5-42.Click the "Next" button to enter the summary page, and click the "Finish" button to complete the addition.

(3) double-click the submodule mychipscope. CDC under mycounter. V in the engineering area to automatically open the Chipscope Pro Core Insterser software and add the trigger unit and the trigger bit width.The trigger type was selected as Basic, with a bit width of 8 bits.Set the sampling depth to 4096, as shown in figure 5-43 to figure 5-46.

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Figure 5-43 debugging project configuration interface

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Figure 5-44 ICON core configuration interface

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Figure 5-45 trigger signal configuration interface

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Figure 5-46 acquisition depth configuration interface

(4) click "Next" to enter the network list connection display page, as shown in figure 5-47.If the trigger and clock signal line defined by the user are not connected, the words "UNIT", "CLOCKPORT" and "TRIGGERPORTS" will be displayed in red.When the connection is completed correctly, it turns black.

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Figure 5-47 netlist connection prompt interface

Click the "Modify Connection" button in figure 5-47 to enter the Connection page. The Connection of clock and data is shown in figure 5-48 and figure 5-49.It should be noted that ChipScope Pro can only analyze internal signals designed by FPGA, so it cannot be directly connected to the input signal network list, so the input signal network list is all shown in grey.If the input signal is to be sampled, it can be realized by connecting its input buffer signal. The clock signal selects the corresponding BUFGP, and the ordinary signal selects the corresponding IBUF.As shown in figure 5-48, when the sampling clock is selected, CLK_BUFGP is selected.

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Figure 5-48 clock netlist connection interface

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Figure 5-49 trigger netlist connection interface

When the connection is complete, click "OK" to Return to the connection display screen, and find that all prompt characters "UNIT", "CLOCKPORT" and "TRIGGERPORTS" are not red. Click "Return Project Navigator" to exit Chipscope and Return to ISE.Otherwise, click the "Modify Connection" button again to reconnect.

(5) UCF files are added to the project to constrain the positions of clocks and data pins.In order to simplify, only the pin constraints of CLK and reset can be added, which are as follows:

NET "CLK" LOC = "C9"

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NET "CLK" PERIOD = 20.0ns HIGH 40%;

NET "reset" LOC = "H13" | IOSTANDARD = LVTTL | PULLDOWN;

(6) double-click "Implement Design" and "Generate Programming File" in the ISE process control area to complete the implementation and Generate programmable files, and all kinds of cores inserted by designers will also be included in the bit files.Once the configuration file is generated, double-click the Analyze Design Using Chipscope icon shown in figure 5-50 to automatically open the Chipscope Pro Analyzer software.

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Figure 5-50 schematic diagram of Chipscope Pro Analyzer startup operation

(7) click the icon "" on the toolbar on the Chipscope Analyzer user interface to initialize the boundary scan chain.After the scan is completed, click "DEV: 0 My Device0(XC3S500E) → Configure" under the "Device" menu to select the command.

(8) after the chip configuration is completed, select the "Import" command from the "File" menu, and the CDC File loading page will pop up. Select the corresponding CDC File, which will change all the names of "Dataport" to the integrated network names.

(9) combine CNT bus signals.Hold down "Ctrl" key to select multiple Bus signals, right click and select "Add to Bus" command to combine them into corresponding Bus signals, as shown in figure 5-51.

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Figure 5-51 operation diagram of adding bus

(10) do not set trigger conditions to collect data.Click the "" icon in the toolbar to start collecting data.The overall result is shown in figure 5-52. Click the "" button in the toolbar to amplify the signal. The partial result is shown in figure 5-53.It can be seen from the analysis results that the design successfully completed the function of 8-bit counter in FPGA.

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Figure 5-52 overall schematic diagram of Analyzer analysis results

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Figure 5-53 local schematic diagram of Analyzer analysis results

(11) set trigger conditions to collect data.Enter the Trigger condition "0000_0000" in the Value column of "M0: Trigger Port0" in the Match field of "Trigger Setup" column, as shown in figure 5-54.

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Figure 5-54 trigger condition setting interface

Click the "" icon in the toolbar to start data collection. It can be seen that the first number of collection results is 0, as shown in figure 5-55.Of course,users can set more complex triggering conditions as needed.

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Figure 5-55 trigger condition setting interface

(12) use Bus Plot function to Plot the output signal waveform.Double-click the "Bus Plot" command in the engineering area, then select "dout" in the "Bus Selection" section of the pop-up window, and the collected data will be displayed graphically, as shown in figure 5-56.Since this design is an 8 bit plus 1 counter, its waveform is a sawtooth wave with amplitude from 0 to 255.

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Figure 5-56 waveform diagram of 8 counter

 

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