Difference and connection between SPI, UART and IIC bus
Update Time: 2021-06-21 10:55:06
SPI (Serial Peripheral Interface) is a high-speed, full-duplex, synchronous, serial communication bus with a 3~4-wire interface that works in master-slave mode and sends and receives independently, allowing multiple SPI devices to be connected to each other.
The SPI device that provides the SPI serial clock is the SPI host or master device (Master), and the other devices are SPI slaves or slave devices (Slave).
The SPI bus consists of three signal lines, SCLK (Serial Clock), SDI (Serial Data Input), and SDO (Serial Data Output). When there are multiple slave devices, you can also add a slave device selection line, CS is to control whether the chip is selected, so that multiple SPI devices can be connected to each other on the same bus.
If the GPIO port is used to emulate the SPI bus, there must be an output port (SDO), an input port (SDI), and another port depending on the type of device implemented. If you want to implement a master-slave device, you need the input and output ports, and if you implement only a master device, the output port is sufficient, and if you implement only a slave device, you only need the input port.
SDI - master device data input, slave device data output.
SDO - master device data out, slave device data in.
SCLK - clock signal, generated by the master device.
CS - slave device enable signal, controlled by the master device.
SPI is a protocol that allows a master device to initiate a synchronous communication with a slave device, thus completing the exchange of data. SPI is a serial protocol, which means that data is transmitted bit by bit, which is why the SCLK clock line exists, and the SCLK provides the clock pulses on which SDI and SDO complete the data transmission.
The data output is via the SDO line and the data changes on the rising or falling edge of the clock and is read on the immediately following falling or rising edge. The same principle is used for the input to complete the one-bit data transfer.
In this way, the transfer of 8 bits of data is completed with at least 8 changes of the clock signal (once for the rising and falling edges).
One advantage of such a transmission method is that unlike normal serial communication, which continuously transmits at least 8 bits of data at a time, SPI allows data to be transmitted one by one, even allowing pauses, because the SCLK clock line is controlled by the master device and the slave device does not collect or transmit data when there is no clock jump. In other words, the master device can complete control of the communication by controlling the SCLK clock line.
SPI is also a data exchange protocol: because the data input and output lines of SPI are independent, it allows data input and output to be done simultaneously. The implementation varies from one SPI device to another, mainly because the timing of data change and acquisition varies, and there are different definitions for acquisition at the upper or lower edge of the clock signal, please refer to the documentation of the relevant device for details.
Finally, one disadvantage of the SPI interface: there is no specified flow control and no answering mechanism to confirm whether data is received.
In point-to-point communication, the SPI interface does not require addressing operations and is full-duplex, making it simple and efficient. In multiple slave systems, each slave device requires a separate enable signal and is slightly more complex in hardware than an I2C system. the SPI interface is mainly used between EEPROM, FLASH, real-time clocks, AD converters, and digital signal processors and digital signal decoders.
The UART (Universal Asynchronous Receiver Transmitter) bus is a two-wire, full-duplex, asynchronous serial interface with slow speed. It is much more complex than the structure of SPI and I2C, two synchronous serial ports, and generally consists of a baud rate generator (the generated baud rate is equal to 16 times the transmission baud rate), UART receiver, and UART transmitter, with two wires in hardware, one for transmitting and one for receiving.
The data is transmitted asynchronously, the timing requirements for both sides are strict, and the communication speed is not very fast, so it is most used on top of multi-machine communication. If you use GPIO port to simulate UART bus, you need one input port and one output port.
UART is the chip used to control the computer and serial devices. It provides an RS-232C data terminal device interface so that the computer can communicate with modems or other serial devices that use the RS-232C interface.
Most computers contain two RS232-based serial ports. The serial port is also a common communication protocol for instrumentation devices; many GPIB-compatible devices also have RS-232 ports. Also, serial communication protocols can be used to acquire data from remote acquisition devices.
The concept of serial communication is very simple; serial ports send and receive bytes by bit. Although slower than byte-by-byte parallel communication, the serial port can send data on one wire while receiving data on the other. It is simple and enables communication over long distances.
As part of the interface, the UART also provides the following functions.
Converting parallel data transmitted from inside the computer into an output serial data stream.
Converting serial data coming from outside the computer into bytes for use by devices that use parallel data inside the computer.
Adding parity bits to the output serial data stream and parity-checking the data stream received from outside.
Adding start-stop marks to the output data stream and removing start-stop marks from the received data stream.
Handling interrupts signaled by the keyboard or mouse.
the possibility of handling the synchronization management of the computer with external serial devices.
There are some higher-end UARTs that also provide buffers for input and output data. A relatively new UART is now the 16550, which can store 16 bytes of data in its buffer before the computer needs to process it.
The IIC (Inter-Integrated Circuit) bus is a bi-directional, two-wire (SCL, SDA), synchronous, serial, multi-master interface standard with contention detection and bus arbitration mechanisms, ideal for close, non-recurring data communication between devices.
In the IIC protocol system, data is transmitted with the device address of the destination device, so device networking is possible.
If the GPIO port is used to emulate the IIC bus and realize bi-directional transmission, an input-output port (SDA) is required, and an additional output port (SCL) is required.
The main advantage of the IIC bus is its simplicity and effectiveness. I2C can be used as an alternative to the standard parallel bus and can connect various integrated circuits and functional modules. Only two bus lines are required: one serial data line SDA and one serial clock line SCL.
IIC is a multi-master bus, where each device on the bus has a unique address, and depending on the device's own capabilities, any device capable of transmitting and receiving can work like a master and control the bus. Of course, there can be only one master at any point in time, and if two or more hosts initialize data transmissions at the same time they can be prevented from being corrupted by conflict detection and arbitration.
One master is able to control the transmission of signals and the clock frequency. Synchronous clocks allow devices to communicate over the bus at different baud rates. The synchronous clock can be used as a handshaking method to stop and restart serial port transmissions.
Because the interface is directly on top of the component, the I2C bus takes up very little space, reducing board space and the number of chip pins, and reducing interconnection costs. The bus can be up to 25 feet long and is capable of supporting 40 components at a maximum transfer rate of 10Kbps.
Serial 8-bit bi-directional data transfer bit rate
Up to 100kbit/s in standard mode
Up to 400kbit/s in fast mode
Up to 3.4Mbit/s in high speed mode
IICs use pull-up resistors and are weakly immune to interference, and are generally used for communication between chips on the same board, and less often for long-distance communication. The number of ICs connected to the same bus is limited only by the maximum capacitance of 400pF of the bus.