Design of TMS320VC33 chip and CPCI bus for module acquisition and control functions
Published time: 2020-03-30 12:05:38
In the field of industrial control, in order to achieve acquisition and control functions, A / D and D / A modules are often used. In actual use, there are many options for the communication method between A / D, D / A module and host. Such as RS 232, RS 422, network and other interface methods. In this design, the A / D, D / A module communicates with the host through the CPCI bus, collects data through the A / D interface, processes it with servo control software, and outputs analog quantities to drive the actuator.
In order to achieve a closed-loop control. In addition, by modifying the DSP software, this module can also independently implement A / D or D / A functions.
The A / D and D / A modules in this design have the following functions:
(1) Provide 2 16-bit A / D, input signal range ± 5 V, accuracy requirement is less than ± 16 LSB;
(2) Provide 2 16-bit D / A, output signal range ± 5 V, accuracy requirement is less than 8 LSB, subject to system reset control;
(3) Use TI's DSP (TMS320VC33) as the onboard processor. This DSP mainly implements the functions of managing A / D and D / A, running control algorithms, and communicating with the host, and is controlled by system reset;
(4) DSP and host adopt dual-port RAM (IDT7133) to realize data exchange function.
This module uses TI's high-performance CPU device TMS320VC33 as the core. The module is connected to the CPCI bus through the PCI9052 chip, and the signal of the local bus of the PCI9052 is connected to one end of the dual-port RAM. The other end of the dual-port RAM is connected to the DSP through a level buffer.
The DSP core circuit consists of DSP chip TMS320VC33, data RAM CY7C1041VC33, and program FLASH chip SST39VF800A; the address, data, and control bus of the DSP are connected to dual-port RAM, A / D chip, D / A chip, and CPLD through level buffer devices. The DSP exchanges data with the main control computer through the dual-port RAM chip; the initialization and reading and writing operations of the A / D chip are also completed by the DSP; the DSP controls the D / A chip to output analog signals; the CPLD mainly implements the combined logic function and converts the DSP The input control signal is decoded and then output to dual-port RAM and A / D, D / A and other functional chips.
The dual-port RAM chip is an important component for realizing the smart board. Because the address space resources of the DSP and the host computer are independently allocated, they cannot directly access each other. A data buffer is required between the two. The characteristics of dual-port RAM Make it meet this requirement.
2.1 Selection of main components
In this design, mature technology is used, and commonly used and reliable control chips are selected, combined with some commonly used peripheral circuits and dedicated circuits to achieve all functions. That is, PC19052 is selected as the interface chip, and the chip is used to implement the PCI bus slave interface logic.
TMS320VC33 was selected as the on-board processing chip. This chip is a high-performance DSP specially developed by TI for floating-point operations. It has a strong data processing capability and contains rich peripheral circuit expansion interfaces.
In order to realize the level conversion function on the module, SN74ALVC164245DL, which is widely used, is selected as the level conversion buffer chip.
2.2 PCI9052 and dual-port RAM hardware interface implementation
As shown in Figure 1, the local bus signal that connects the PCI9052 to the dual-port RAM includes address, data, and control signals. The address bus width is 12 bits, and the data bus width is 16 bits, so the address space is 2 KB of 16 b address space. The control signals include read-write control signals and peripheral preparation completion signals. After the dual-port RAM pulls the peripheral preparation completion signal low, the host can read and write the dual-port RAM by outputting read-write control signals.
Figure 1: DSP signal link diagram
2.3 DSP design core circuit design
DSP is the core of the whole design. The DSP core circuit is composed of DSP chip, FLASH and RAM. The DSP exchanges data with the processing computer through dual-port RAM.
As shown in Figure 1, the DSP core circuit design is as follows. The DSP's power supply includes two core operating voltages of 1.8 V and I / O voltage of 3.3 V, which are provided by the on-board power module. The clock signal is provided by an external crystal. The reset signal is provided by the CPLD. Since the I / O voltage of the DSP is 3.3 V, it needs to perform level conversion between 3.3 and 5 V when it is connected to a signal with an I / O level standard of +5 V. The interrupt signal is also connected to the CPLD through the level-shifting device. The address and data buses connect functional devices according to the needs of the actual design. The JTAG interface is connected to a standard dual in-line 14-pin in-line connector of the module. Page0 ~ 3 signals are connected to the CPLD through level shifting devices.
2.4 Power supply design
The system power supply includes +5 V. 3.3 V, 1.8 V, +15 V, -15 V.
The core voltage of the DSP chip is 1.8 V, and the I / O voltage is 3.3 V, so the board is required to provide two voltage sources, 3.3 V and 1.8 V. The D / A chip needs to provide two power sources: +15 V and -15 V. +5 V power is provided by the system, and other power is obtained by +5 V power conversion.
For linear voltage regulator, its characteristics are simple circuit structure, small number of components required, and input / output voltage difference can be large, but its fatal weakness is low efficiency and high power consumption. The DC-DC circuit is characterized by high efficiency, flexible buck-boost, and shortcomings of large interference and ripple.
Compared with the same type of voltage conversion chips from Linear Technology, National Semiconductor, and Texas Instruments, Texas Instruments' TPS73HD318 module was selected as the 3.3 V and 1.8 V voltage conversion chips. Select RECOM male: REC3-0515DRW to complete the voltage conversion between +5 V and +15 V, -15 V. They have a conversion efficiency of more than 90%, simple peripheral circuits, a smaller package, and a ripple voltage of less than 2.5%.
2.5 Reset design
The reset input includes two parts: RESETA output by MAX1232 and RESETB output by power chip TPS73HD318. The inputs of MAX1232 are manual reset signal input and watchdog feed signal input. The manual reset signal comes from the reset button, and the dog feed signal comes from CPLD. The reset outputs 2 signals to the DSP and D / A respectively.
2.6 Level Translation Design
Because the interface level of the DSP is 3.3 V and the interface level of the CPLD and PC19052 is 5 V, in order to make the two parts compatible, a level-shifting buffer chip is needed. The device has two power supplies, two direction control terminals, and two enable terminals. By connecting different voltage sources, different levels can be provided for the signal pins of the device.
2.7 A / D, D / A design
The A / D and D / A chips are connected to the DSP's address data bus through the level buffer period. The DSP chip is responsible for the initialization and read-write control of the A / D and D / A.
3, CPLD logic design
There are three main functions implemented in the CPLD, the logical interface with the DSP bus, internal registers, and control logic.
The interface logic of the DSP bus is implemented with the DSP logic interface, so that the DSP can access the internal registers of the CPLD. The status register is a read-only register that is used to read the interrupt status and flag bits for communication with the dual-port RAM; the control register is a write-only register that is used to control the interrupt mask and modify the communication flag bits. Combinational logic is mainly used for address decoding, read-write decoding.
4.DSP software design
DSP software development is mainly under the integrated development environment CCS provided by TI, making full use of the powerful functions of the real-time operating system DSP / BIOS, combined with its own specific processing algorithm, to quickly build a highly efficient software system that meets the needs. In the design, the initialization of the DSP is necessary. This design is mainly used in real-time control systems. The main function of the circuit is to collect, calculate, and output. After power-on, the program stored in the FLASH starts to run, and the DSP starts to initialize the RAM memory, CPLD internal registers, A / D registers, and D / A registers in order. After the initialization is completed, the A / D input is read. Since the A / D conversion speed is slower than the read speed, it is necessary to query the A / D conversion status during the reading process and wait for the A / D chip to output a conversion completion signal. Write the read data to the designated location of the dual-port RAM, and refresh the internal flag bits of the dual-port RAM and CPLD to notify the host to read the data. The A / D data is calculated, and the D / A output is controlled according to the operation result. After the query D / A conversion is completed, the program jumps to read A / D again.
This design is applied to a certain servo control system, which realizes the system function and pays enough attention to the stability and reliability of the system. After a long period of evaluation, the system runs stably and reliably.Tag: TMS320VC33