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Home > Processor/DSP > Design of a data acquisition system based on the combination of DSP te

Design of a data acquisition system based on the combination of DSP technology and USB communication technology

Update Time: 2020-08-17 14:49:40

Nowadays, there are many data acquisition systems, some are based on digital signal processor DSP, and some are based on field programmable gate array FPGA. Although these acquisition systems have good data acquisition and processing capabilities, most of them adopt traditional timing mode.

The remote synchronous measurement is a method often used in engineering. If the traditional time service mode is used, the clock frequency is generated by a crystal, and the crystal will age, and it is susceptible to changes in the external environment and long-term accuracy drift, resulting in a decrease in timing accuracy. In fact, the data measured in such a remote location is no longer synchronized in theory and at the same time. This system adopts a new GPS time service method, and a data acquisition system designed with DSP technology and USB communication technology can better solve this problem.

1 The overall hardware composition and working principle of the data acquisition system

The data acquisition system is composed of analog input, synchronous sampling control, A/D conversion, microprocessor and interface, as shown in Figure 1.

Figure 1 Block diagram of the overall hardware structure of the data acquisition system (2).png

The analog input part has multiple channels (such as 16 channels), which can be used to measure several voltages and several currents at the same time. The voltage or current from the secondary side of PT or CT is sampled by the synchronous sampling system based on GPS time base after isolation conversion and analog low-pass filtering, and then sequentially put into fixed RAM area after sequential A/D conversion. According to the recursive DFT algorithm, DSP calculates all measured fundamental components of each phase at each new sampling point, and then uses the time information provided by the serial port of the GPS receiver and the sequential number of the first sampling point of the data window to give the calculation result Place a "time stamp" for easy identification. The calculated phasors and their time tags are sent to the PC host computer for processing and analysis through the DSP bus and USB2.0 data line in accordance with a certain data format.

2 Synchronous sampling control unit based on GPS timing

Synchronous sampling is the key technology to realize remote synchronous measurement. Only when the sampling of each measurement point is synchronized, the phasor calculated at the same time has a unified reference time base, and the phase relationship can be directly compared. This article discusses six different timing methods: radio broadcasting, LORANC, OMEGS, GOES, GLO-NASS, and GPS. The error comparison of these timing methods is listed in Table 1.

Error comparison table of timing method.png

Through comparison, it is not difficult to see that traditional clock synchronization methods are difficult to meet the requirements of remote synchronization measurement in terms of accuracy and practicability due to technical and economic factors; only the superior performance of GPS precision timing methods meets the requirements. For this reason, what this article introduces is a newest clock synchronization method based on GPS time signal.

2.1 Introduction to GPS system

GPS is the second-generation satellite navigation system developed by the United States. The GPS system consists of a space part, a ground control part and user equipment. The space part is mainly composed of 21 working satellites and 3 spare satellites. At least 3 satellites can be seen anywhere on the earth (with a 360° field of view) (according to the actual situation of the author). The ground control part includes the monitoring station, the main control station and the injection station. The user equipment is the GPS receiver. The receiver selected by this system is the GPS-OEM board (the model is GPS15L, which will be discussed in detail in section 2.3). It calculates where the receiver (antenna) is based on its own clock and the received navigation message Location and GPS time.

2.2 GPS timing principle

The current timing GPS receiver will give a 1 pps (second pulse) signal synchronized with UCT time and its corresponding time code after its internal clock is synchronized with GPS time, as shown in Figure 2.

GPS receiver output 1pps schematic diagram (2).png

2.3 Synchronous sampling control unit hardware

When designing this module, the GPS15L OEM board and microcontroller AT89C51 developed by Garmin were selected as the GPS receiver and controller respectively. This module embodies the GPS timing technology used in the entire system. The working principle is as follows: After the system is powered on and reset, the single-chip microcomputer realizes the initialization of the GPS15L board through the serial port TXD and sets the data format transmitted by the GPS receiver. After the initialization is completed, the GPS15L board will give corresponding information. After the single-chip microcomputer recognizes the information, it will start to receive the time data sent by the GPS15L board, process it, and convert it into Beijing time output. As shown in Figure 3, the serial ports RXD and TXD of the AT89C51 microcontroller are respectively connected with the TXD1 and RXD1 of the GPS15L board for communication. Since TXD not only needs to send the initialization command to the GPS15L board when the power is turned on, but also transmits Beijing time after the initialization is completed, so in order not to make the work of the two stages affect each other, the P1.0 port line and several logic gates are used to control the communication. Priority. After the GPS15L board is initialized, it will output a second pulse signal. The 1pps signal has one channel as the external interrupt source of the single-chip microcomputer to realize the synchronization processing of time information, and it is also used to monitor whether the signal is normal. There is also a signal that can be controlled by the P1.1 port of the single-chip microcomputer, and it is determined whether it needs to be transmitted to the next-level controller according to the monitoring result.

In addition, the high-stability crystal oscillator used in this circuit is an OCXO-type stabilized crystal oscillator with a working frequency of 1 MHz and a frequency difference of not more than 10-7. The oscillating signal output by it is reshaped and level converted to a level suitable for the TTL circuit. After frequency division by the counter, a clock signal that meets the sampling rate requirements is obtained (the sampling rate is adjustable). The clock signal is synchronized by the rising edge of the 1 pps signal every 1 s to make it run on the GPS time reference. Because the stability of the 1 MHz crystal oscillator is very high, the drift within 1 s does not exceed 1 μs, so the synchronization sampling pulse accuracy obtained is very high.

Figure 3 The principle block diagram of the GPS synchronous sampling control unit.png

3 Interface part of ADC and DSP

The DSP chip adopts the digital signal processor TMS320F2812PGFA developed by Texas Instruments. It is a 32-bit fixed-point arithmetic, high integration, and cost-effective DSP chip.

The data acquisition system selectsADS8361 as the off-chip ADC module. Although TMS320F2812 has 16-channel 12-bit ADC, in order to further improve the system’s A/D conversion accuracy, an off-chip peripheral ADS8361 is added. ADS8361 is a 2+2 channel, 16-bit A/D converter; it is fully compatible with ADS7861 (12-bit) and can be directly interfaced with the F2812 digital signal processor. It is divided into two groups of four-channel differential inputs and connected to independent converters, which can complete simultaneous acquisition of dual signals, and the maximum conversion rate can reach 500 kHz. It has a strong anti-interference ability when working at a frequency of 50 kHz, which is especially suitable for occasions with high sampling rate requirements for data acquisition. In addition, ADS8361 also provides a high-speed dual serial interface, which can effectively reduce software overhead, and the power consumption is very low, only 150 mW.

3.1 ADS8361 and TMS320F2812 interface circuit design

The TMS320F2812 processor provides a multi-channel buffered serial port (McBSP) and a serial peripheral interface (SPI), both of which can interface with the ADS8361. According to the needs of the design, this system adopts the McBSP interface expansion method. In the interface hardware design of ADS8361 and TMS320F2812, in order to avoid the data signal to produce the ringing, specially consider to increase the absorption resistance between DSP and ADS8361. Since TMS320F2812 has only one McBSP interface, ADS8361 must be set in mode 2 and mode 4. The hardware interface circuit of TMS320F2812 and ADS8361 is shown as in Fig. 4. The CLOCK, (RD+CONVST) and SDA pins of ADS8361 are respectively connected to the CLKX, (FSX+FSR) and DR pins of McBSP. Since only one A/D conversion chip is connected to McBSP, the chip select signal (CS) is directly grounded, if you need to expand multiple A/D conversion chips, you can use GPIO to control the chip select signal; at the same time, use general I/O to control the ADS8361 Working mode, make M0=0, M1=1; DX controls the channel selection of ADS8361.

ADS8361 and TMS320F2812 interface circuit diagram.png

3.2 Design of analog input signal conditioning circuit

After the phase current and phase voltage of the power system are transformed by CT and PT respectively, the output is a standard ±10 V analog voltage signal. This analog voltage signal needs to pass through a front-end low-pass filter to filter out unnecessary high-frequency noise signals, and to transform the analog input signal range from ±10 V into a signal range acceptable to the back-end A/D. The analog conditioning circuit of each channel is shown in Figure 5.

Figure 5 Analog input conditioning circuit.png

4 USB interface communication circuit part

The communication circuit adopts the USB interface, and the USB interface chip is CY7C68001 of Cypress. The connection circuit of CY7C68001 and TMS320F2812 is shown as in Fig. 6.

CY7C68001 and TMS320F2812 connection circuit diagram.png

As the peripheral of TMS320F2812, CY7C68001 uses asynchronous memory interface to connect with TMS320F2812. The upper PC can wake up CY7C68001, or it can be equipped with USB chip. USBCS is the chip selection signal line of CY7C68001. When USBCS is low level, CY7C68001 uses asynchronous reading and writing to complete the exchange of data and commands between the two.

CY7C68001 has two external interfaces, namely FIFO data interface and command port. The data acquisition system configures these two external interfaces in the address range of 0x004000~0x004004, and the allocation is listed in Table 2. TMS320F2812 can visit the data in 4 1 KB FIFO through the FIFO data interface of CY7C68001, and the choice of FIFO data interface is realized by controlling the address line A[2:0]. When the address line A[2:0] of TMS320F2812 is 100B, select the command port of CY7C68001, and then through the command port you can access 37 registers, Endpoint0 buffer (64-byte FIFO) and description table (500-byte FIFO), etc. . If the Endpoint0 buffer and description table are also regarded as registers, then a single command port contains many registers, and read/write access to these registers adopts secondary addressing, that is, the register to be addressed through the command port. Write the address and operation type (read operation or write operation), and then read or write the data into the corresponding register through the command port.

CY7C68001 also has an interrupt signal USBINT and 4 status signals (USBREADY, FLAGA, FLAGB, and FLAGC). The interrupt signal USBINT occupies the external interrupt XINT1 of the TMS320F2812, and the status signals USBREADY, FLAGA, FLAGB and FLAGC are configured in another extended register. TMS320F2812 can query it to obtain the status of the USB. The WAKEUP of the USB chip is also configured in another extended register, and TMS320F2812 achieves the purpose of waking up the USB by writing to this register.

5 The software part of the system

The software part of the system includes the main program and each interrupt program and the USB communication program between the system and the upper PC. The main program completes the initialization of each variable and serial port, and uses the Fourier transform algorithm to calculate the real and imaginary parts of each sampling point. The interrupt program includes A/D conversion program, GPS time information reading program, etc. 

6 Power supply design

The power supply circuit adopts a derating design and adopts a high-precision power supply circuit to ensure the reliability of the power supply system.

① The internal reference power supply of ADS8361 is +2.5 V.

② The power supply voltage of GPS15L OEM board is 3.3 ~ 5.4 V, and the power supply voltage of GPS receiving antenna is 3.0 V.

③ TMS320F2812 requires dual power supplies (1.9 V and 3.3 V) to supply power for CPU, Flash, ROM, ADC and I/O interfaces.

When powering on, in order to ensure the correct reset of each module in the chip, the TMS320F2812 power supply needs to meet a certain timing. The system first powers on all +3.3 V power supply pins (VDDIO, VDD3VFL, VDDA1, VDDA2, VDDREF), and then turns on the chip core power supply of 1.9 V (VDD, VDD1); when the voltage of VDDIO rises to 2.5 V , VDD rises to 0.3 V, so as to ensure that each module on the chip can be reset correctly when powered on. At power down, the system resets before VDD drops to 1.5 V. Only in this way can the on-chip Flash module be reset correctly before VDD and VDDIO are powered down. In this system design, the dual power output, Low-Dropout power supply TPS76801QDR provided by TI is selected to supply power to the TMS320F2812 to achieve the above-mentioned power supply sequence.

Conclusion

This data acquisition system has four channels, the A/D conversion accuracy is 16 bits, the conversion accuracy is high and the anti-interference ability is extremely strong, and the collected data can be transferred in real time via USB. In addition, the most important thing is to use GPS time service mode instead of traditional time service mode, which is especially suitable for occasions that require synchronous collection in different places. For example, in the electrical parameters of high-speed electrified railways, in order to obtain the train current, position, rail potential, rail current, and current on the line simultaneously, it is only necessary to use the same data acquisition system at the two measurement points on the train and the rail ground simultaneously. In this way, the measured phasor data has a unified time reference, which is convenient for scientific analysis of these parameters.


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