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Home > Other > Broadcom Expands Collaboration with Synopsys on 7nm and 5nm Designs

Broadcom Expands Collaboration with Synopsys on 7nm and 5nm Designs

Update Time: 2021-04-27 18:10:52


Broadcom Expands Collaboration with Synopsys on 7nm and 5nm Designs

Extensive use of Synopsys Fusion Design Platform to accelerate market shaping solutions


Synopsys provided Broadcom with an optimized 7nm design flow and methodology to enable high-volume designs based on Fusion Design Platform

Best-in-class digital implementation tools, including Fusion Compiler, IC Compiler II, Design Compiler NXT, PrimeTime and StarRC families, provide new opportunities for 5nm chip differentiation

(NASDAQ: SNPS) recently announced an extended partnership with Broadcom Inc. to help Broadcom develop semiconductor solutions based on Fusion Design Platform to address a range of design challenges at 7nm and below.

Building on multiple successful experiences with 7nm designs, Broadcom and Synopsys have further collaborated to deploy 5nm chip designs including those based on Fusion Design Platform. By integrating Synopsys' tools, processes and methodologies, Broadcom is maximizing the benefits from the latest chip process offerings and effectively delivering value to its customers.

Broadcom is excited to collaborate with Synopsys on 7nm and 5nm chip designs and to continue working together with Synopsys to deliver high-volume designs using Fusion Design Platform," said Yuan Xing Lee, vice president and head of engineering at Broadcom Center. As a global leader in infrastructure technology, Broadcom continues to pursue innovation excellence and is committed to delivering highly differentiated products that help customers differentiate themselves in their respective markets."

Fusion Design Platform is designed to help design teams achieve the best power, performance and area (PPA) in the most convergent manner to ensure the fastest and most predictable time-to-results (TTR).Fusion Design Platform spans test insertion and optimization, RTL synthesis, layout routing, and design convergence and Fusion Design Platform enables a new level of predictable PPA that addresses the industry's inherent chip design challenges.

Working closely with our partners is key to ensuring that our customers get the most equity and value from the latest chip processes," said Sassine Ghazi, general manager of Synopsys' Chip Design Business Unit. Synopsys and Broadcom are in a long-term partnership and together we will maintain our vision of mutual success and enhance our respective execution in delivering differentiated value to ensure that together we can deliver best-in-class technologies, products."

Key products and features of the Synopsys Fusion Design Platform include.

Fusion Compiler RTL-to-GDSII solution: Highly optimized full-flow support for optimal design scalability and convergence and the shortest time to results (TTR)

IC Compiler II layout and routing: EUV single-exposure routing with optimized 5LPE design rule support, single fin variant-aware legalization, and via stapling to ensure maximum utilization and minimum dynamic power consumption

Design Compiler® NXT RTL synthesis: correlated consistency of results, wiring congestion reduction, pin-aware access optimization, 5LPE design rule support, and physical guidance for IC Compiler II

PrimeTime® timing signoff: near-threshold ultra-low voltage variant modeling, over-hole variant modeling, and engineering change order (ECO) guidance for perceptual layout rules

StarRC parasitic parameter extraction: support for EUV single-exposure based wiring, and new extraction techniques such as overlay-based modeling of vias and vertical gate resistances

Tag: Broadcom

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