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Home > Other > Application scheme of image acquisition system based on FPGA device EP

Application scheme of image acquisition system based on FPGA device EP2C5F256C6 chip

Published time: 2020-08-25 11:15:38

Introduction

In low-speed data acquisition systems, microcontrollers or DSPs are often used for control; but for high-speed data acquisition situations such as image acquisition, this solution cannot meet the needs. Therefore, this scheme greatly wastes the port resources of the single-chip microcomputer or DSP and has poor flexibility; if the serial port method is used to collect data, on the one hand, the data collection speed is reduced, and on the other hand, the CPU resources are greatly consumed. This system uses FPGA as the main control unit for data acquisition, and all control logic is completed by hardware, with fast speed, low cost and strong flexibility. In order to increase the buffer function, the system expanded 256Mb of RAM outside the FPGA, which not only increased the buffer capacity, but also greatly reduced the frequency of reading and writing, effectively reducing the burden on the host computer CPU. Among the image data interfaces, VGA and PCI-Express are more common, and these interfaces have poor scalability and high cost. This system uses a high-speed USB interface as the communication port with the host computer, which is fast, easy to install, and flexible.

1 System block diagram

The system block diagram is shown as in Fig. 1. The FPGA control unit adopts the  EP2C5F256C6 of A1tera's Cyclone II series, which is mainly composed of 4 parts-the main control module, CMOS sensor interface, RAM controller and EZ-USB interface controller. The sensor interface is responsible for completing the SCCB timing control, the RAM controller is used to implement the timing of RAM read and write and refresh operations, the USB interface module completes the data reading and writing between the main control module and EZ-USB; and the main control module is responsible for the slave EZ-USB Part of the received host computer commands are analyzed, and after the commands are parsed, corresponding signals are generated to control various corresponding modules, such as the image format transmitted by the CMOS sensor, the read and write mode of the RAM, and the burst length.

Figure 1 System block diagram.png

2 OV7620 module design

The image sensor uses OV7620, and the interface diagram is shown in Figure 2. The sensor is powerful, provides output in multiple data formats, automatically eliminates white noise, white balance, color saturation, hue control, window size, etc. can be set through the internal SCCB control line. OV7620 belongs to CMOS color image sensor. It supports continuous and interlaced scanning methods, VGA and QVGA two image formats; the highest pixel is 664×492, the frame rate is 30fps; the data formats include YUV, YCrCb, and RGB. 0V7620 supports SCCB setting mode and automatic loading default setting mode, and the selection is controlled by SCCB. This system only needs to support SCCB mode, so SBB is grounded when designing. After power-on, FP-GA sets the OV7620 through the SCCB bus, and the system can also accept commands from the host computer to set its working mode. The SCCB bus timing is similar to the I2C bus timing, SIO-0 is equivalent to SDA, and SIO-1 is equivalent to SCL. OV7620 works in the slave mode. In the process of writing the register, first send the ID address of OV7620, then send the destination register address of the write data, and finally send the data to be written.

Figure 2 OV7620 interface diagram.png

The address of OV7620 function register is 0x00~0x7C, through setting up the corresponding register, can make it work in different modes. For example, to set OV7620 to continuous scan and 16-bit output mode of RGB raw data, you need to set registers 0x12, Oxl3, Ox20, and Ox28 to OX2D, 0x01, Ox02, and 0x20, respectively. In addition, the key issue of image output is frame synchronization. VSYNc, HSYNC, HREF, and PCLK in the VO7620 sensor represent vertical synchronization, horizontal synchronization, reference signal and pixel output synchronization, respectively. Through their cooperation, each frame output can be located. The start bit and end bit of the image.

3 RAM timing control module

The RAM controller interface is mainly used to realize the basic operation timing of RAM, such as charging (refresh) timing, mode setting timing, reading and writing timing, etc. Read and write commands are issued by the main control module and executed by the controller. The system adopts Hy-nix's HY57V561620F(L)T(P), which can realize large-capacity data storage of 256 Mb.

The timing controller is implemented by a finite state machine (FSM), and its state transition diagram is shown in Figure 3. After power-on reset 200μs, all blocks of RAM are precharged, and the pin level of charging operation is listed in Table 1. After charging is completed, all blocks are refreshed by tRP, and the mode setting state is entered after a delay of tRFC. In the mode setting state, it is necessary to set the RAS delay, burst length, etc., enter the idle state after a delay of tMRD, and wait for the read and write commands of the main control unit. In the idle state, all rows in RAM need to be refreshed every 64 ms. In this design, the timing refresh module is designed as a counter, and the count pulse is selected from the clock of the controller itself. Since RAM requires that the maximum time interval between two refreshes does not exceed 64 ms, assuming that the system clock frequency is 100 MHz, the clock cycle is about 0.01 μs, and all 8 192 rows must be refreshed within 64 ms, so the maximum count should be It is 781 times (64 ms/8192/0.01μs). The system uses 700 count pulses to generate refresh requests.

RAM timing control module diagram.png

The read and write address and read and write control signals of the RAM controller are all generated by the main control unit, and the structure block diagram of the main control unit is shown in Figure 4. PLL is used to generate RAM controller and buffer clock (system design is 100 MHz); CMD command analysis module realizes the analysis of commands sent from the host computer and generates corresponding control signals, such as CMOS sensor control, RAM burst length control Wait. In order to reduce the frequency of reading and writing RAM, the system has designed an 8×16-bit FIFO. When the data of 8 pixels is stored in the FIFO, the FIFO sends a write request (W_req) to the RAM controller; at the same time, the write address generator generates the write address, and the RAM controller generates the timing of the write data. The read and write address generator is an incrementing counter, and each read and write address is the last address plus BL (burst length). Since the highest frequency of PCLK can reach 9.2 MHz (640×480×30), and the clock frequency of RAM is 100 MHz, it takes 5 clock cycles to write data of one pixel each time (taking into account the RAS delay), so the write operation consumes the entire 50% of the clock cycle; after adding FIF0, the burst length of read and write is 8, which can reduce the consumed clock cycle to about 10%.

Figure 4 The main control module RAM read and write control structure block diagram.png

4 EZ—USB transfer controller

CY7C68013 is the EZ-USB FX2 series chip of Cypress Company, the pin connection diagram is shown as in Fig. 5. This series of chips integrates USB2.O transceiver, serial interface engine (SIE), enhanced 8501 with 8.5 KB on-chip RAM, 16 KB RAM, 4 KB FIFO memory, I/O ports, data bus, address bus And General Programmable Interface (GPIF); There are 3 interface modes-port mode, slave FIFO interface mode and GPIF interface mode. In port mode, all I/O pins can be used as 805l general-purpose I/O ports. As the most basic data transmission mode, the data transmission is mainly completed by the firmware program and requires the participation of the CPU, so the data transmission rate is relatively low . In slave FIFO interface mode, external logic or external processor can be directly connected to the FX2 endpoint FIFO. The GPIF interface mode uses PORTB and PORTD to form a 16-bit data interface to four FX2 endpoints FIF0 (EP2, EP4, EP6, and EP8). GPIF is directly connected to the FIFO as the internal main controller, and generates user-programmable control signals to communicate with the external interface. The data transmission of the latter two modes is completed by executing the USB protocol itself, and the microprocessor does not participate in the data transmission, so that the data transmission rate is greatly improved.

Figure 5 USB controller pin connection diagram.png

This scheme adopts slave FIFO mode, FPGA provides read and write clock, EZ-USB CPU does not participate in data transmission. Among them, the endpoint FIFO is equivalent to the external RAM of the FPGA, and the reading and writing of data are respectively completed by the reading and writing controller. If data is read into FPGA from EZ_USB, first check the status of CON control line. If there is data to be read, assign FIFOADR=00, make FIFO pointer point to output endpoint, enable SLOE to make data output, and then sample data line The data read is sent to the command analysis module for analysis; if the data is written from FPGA to EZ_USB, set FIFOADR to point to the input endpoint, pull down SLWR, and connect the internal data bus to the external data bus. The data writing is completed once.

In addition to the above design, it is also necessary to set the EZ_USB module itself, which belongs to the firmware development part. Cypress provides a firmware library and firmware framework for firmware development, which are all developed in an integrated development environment. The firmware library provides some constants, data structures and functions to simplify the use of the chip by users. Compile the code in the Keil C51 environment; after the compilation is passed, download the firmware code to the microcontroller. This part mainly completes the setting of related registers and the writing of wave files.

Conclusion

Through the above design, the bottleneck in the sampling and transmission of high-speed data is well resolved, and the collection of high-speed image data is truly realized with a short time delay. Due to its low-cost and easy-to-install features, it has a broad market prospect and can be used in teleconferencing, telemedicine, and remote teaching fields that require high-definition image transmission. The innovative point of this design is that it adapts to the application requirements of different image data and realizes multiple speed read and write modes, which can be real-time burst length read and write and high-speed full page read and write.


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