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Home > Technology List > The introduction of CoolMOS:Advantages , Disadvantages and Main Applic

The introduction of CoolMOS:Advantages , Disadvantages and Main Application

Published time: 2018-06-08

Related knowledge background:

Recently, LLC topology has been highly favored by power supply planning engineers because of its high efficiency and high power density. However, this kind of soft-switching topology requires more MOSFETs than any previous hard-switching topology. Especially in the power starter, dynamic load, overload, short circuit and other circumstances. CoolMOS, with its fast recovery diodes, low Qg and Coss, can fully satisfy these demands and greatly increase the reliability of the power supply system.

A brief description of CoolMOS:

For the conventional VDMOS device structure, the relationship between Rdson and BV is contradictory. To increase BV, we start from reducing the concentration of EPI impurities, but the epitaxial layer is also the channel for positive current flow, and the EPI impurity concentration is reduced. The resistance will inevitably grow, and Rdson will be big. Rdson directly determines the loss of the MOS cell. Therefore, for ordinary VDMOS, the contradiction between the two is not reconcilable, which is the limitation of conventional VDMOS. But for COOLMOS, this contradiction is less obvious. By setting a P zone deeper into the EPI, the BV is greatly increased without affecting Rdson. For the conventional VDMOS, the reverse withstand voltage mainly depends on the PN junction at the interface between the N-type EPI and the body region. For a PN junction, the withstand voltage mainly depends on the depletion region, and the size and consumption of the electric field in the depletion region. Extend the width of the area. The concentration of conventional VDSMO and P body is greater than N EPI. It should be clear to everyone that the depletion region of the PN junction mainly diffuses to the low impurity side. Therefore, under this structure, the P body region side and the depletion region extend very little. Pressure does not contribute much, pressure is mainly P body - N EPI in the N-type side of the area, the electric field intensity of this area is gradually changing, the closer to the PN junction surface, the greater the electric field strength E. For the COOLMOS structure, since the P region with a relatively lower P body concentration is set, the depletion region on the P region side is greatly expanded, and this region is deeply embedded in the EPI, resulting in that both sides of the PN junction can withstand large voltages In other words, the peak electric field Ec is moved closer to the device surface and deeper into the device.

processing strecture_jotrin electronics 

How to select Coolmos Type 

Generally, choosing a MOS to see the following parameters BV, Id, Rds, Vth, Qg, Pd and so on. However, these parameters, as long as Qg and Id are AC parameters, the rest are static parameters. The semiconductor thing is worsening with the temperature rise. That dynamic parameter is actually worse. The current at 25 degrees is 100A, perhaps 125 degrees, and the current is as low as 50A. Therefore, the time of the selection must be based on the data of the high temperature (ageing room). The voltage and current are selected, and the rest is to see the loss of Coolmos. Coolmos has a lower Rdson appearance. As long as the planar tube is 1/3 or 1/4, the MOS conduction loss must be much lower than that of the planar tube. Another loss of MOS, switching loss is often more and more dominant. The most direct value of switching loss in MOS is Trr. This is also the most important parameter of Coolmos. From the perspective of coolmos development, C3C6CPCFDCFD2 is all about Trr. In the practical use of Coolmos, the Rg driver of the MOS front stage generally has a much lower resistance requirement. This also reduces losses. For example, the driving resistance of the front section of the 20N60C3MOS can generally be less than 15mohm, but it is not as low as possible. The higher the switch, the more EMI problems arise. Therefore, the selection of the driving resistor should be considered comprehensively, and the driving resistance should be reduced as much as possible with EMI.

What is the Advantage of Cool-MOS

1. Low on-state impedance and low on-state losses.

Because Rdson of SJ-MOS is much lower than VDMOS, the conduction loss of SJ-MOS must be much smaller than that of VDMOS in use. It greatly improves the conduction loss of the single MOSFET above the system product and improves the system product efficiency. This advantage of SJ-MOS is particularly prominent in high-power, high-current power supply products.

2. The package with the same power specification is small, which is conducive to the improvement of power density.

Firstly, under the same current and voltage specifications, the die area of the SJ-MOS is smaller than the die area of the VDMOS process. As a MOS manufacturer, products of the same specification can be packaged with relatively small-sized products, which is advantageous System power density increases.

Secondly, due to the reduced conduction loss of the SJ-MOS, the loss of the system is reduced, because these losses are dissipated as heat. In practice, we often increase the heat sink to reduce the temperature rise of the MOS cell. It is guaranteed within the proper temperature range. Since the SJ-MOS can effectively reduce the amount of heat and reduce the size of the heat sink, for some slightly lower power systems, even after using the SJ-MOS, the heat sink can be completely removed. Effectively increase the power density of the system.

3. The gate charge is small and the driving ability of the circuit is reduced.

The gate charge of traditional VDMOS is relatively large, we often encounter the temperature rise problem caused by the insufficient driving ability of IC in practical applications. Some products are designed to increase the driving ability of IC and ensure the fast turn-on of MOSFET. We have to add push-pull or other types of drive circuits, which increases the complexity of the circuit. The gate capacitance of the SJ-MOS is relatively small, so that it can reduce its requirement for the drive capability and improve the reliability of the system product.

4. Small capacitance, fast switching speed, and low switching loss.

Due to the change of the SJ-MOS structure, the output capacitance of the SJ-MOS is also greatly reduced, thereby reducing the loss during turn-on and turn-off. At the same time, due to the reduced response of the SJ-MOS gate capacitance, the charging time of the capacitor is shortened, which greatly increases the switching speed of the SJ-MOS. For fixed-frequency power supplies, the turn-on and turn-off losses can be effectively reduced. Improve the efficiency of the entire power system. This is especially true in circuit systems with relatively high frequencies.

What is the difference between Coolmos and ordinary MOSFET

1 shape comparison:


 standard mosfet 

The trench gate MOS transistor shortens the "T" conductive path in the VDMOSFET into two parallel vertical conductive paths, thereby reducing the resistance.

The trench gate MOS transistor shortens the "T" conductive path in the VDMOSFET into two parallel vertical conductive paths, thereby reducing the resistance. 

Coolmos is a vertically highly doped N+ diffusion region between two vertical P wells that provides a low-resistance path for electrons, reducing the on-state resistance.

What is the application of Cool-MOS

1.EMI may exceed the standard.

Due to the small parasitic capacitance of the SJ-MOS, the super junction MOSFET is created with extremely fast switching characteristics. Because of this fast switching behavior with extremely high dv/dt and di/dt, switching performance is affected by parasitic components in the device and printed circuit board. For a modern high-frequency switching power supply, using a super-junction MOSFET, the EMI interference will certainly increase. For a power supply board with a relatively small design margin, the SJ-MOS will surely exceed the EMI limit in the process of replacing the VDMOS. Happening.

2. The grid oscillates.

Gate ringing due to lead inductance and parasitic capacitance of the power MOSFET due to the high switching dv/dt of the super junction MOSFET. Its turbulence will be more prominent. This oscillation can cause serious problems during startup, overload conditions, and parallel operation of the MOSFETs, resulting in the possibility of MOSFET failure.

3. Poor surge and pressure resistance.

Due to the structural reasons of SJ-MOS, many manufacturers of SJ-MOS in the practical application of the process to promote the replacement of VDMOS, the basic surge and withstand voltage test failed. This situation is even more pronounced in power supplies with higher power requirements and lightning strikes. This must attract our attention.

4. The drain-source voltage spike is relatively large.

Especially in the flyback circuit topology power supply, due to the circuit itself, the leakage inductance of the transformer, the grounding of the heat sink, and the handling of the power supply ground wire, it is inevitable to generate corresponding voltage spikes on the MOSFET. In response to such problems, the flyback power supply mostly uses the RCD SUNBER circuit for absorption. Because SJ-MOS has a faster switching speed, it is bound to cause higher VDS spikes. If the back pressure design margin is too small and the leakage inductance is too large, after replacing the SJ-MOS, the VD peak failure problem is most likely to occur.

5. Ripple noise

Because SJ-MOS has high dv/dt and di/dt, it will inevitably couple the MOSFET spike to the secondary through the transformer, which will directly increase the output voltage and current ripple. Even caused the problem of temperature rise failure of the capacitor.

6.The opinion of the official engineer of jotrin electronics.

Ben, Electronics Engineer from Jotrin Electronics said:"With the upgrading of products coolmos, the requirements for the circuit will be more integrated, so the components can be developed to higher power and smaller size. The main idea of Coolmos is to seek: the lowest loss of the switch. On the Coolmos, it passes through the P-pillar to form a larger PN junction and then drops Rds. Decrease Rds, EAS can be lower than the flat tube. However, because the price of COOLMOS is too expensive, which is 1-2 times higher than VDMOS (planar MOS), various manufacturers and engineers are also trying to avoid COOLMOS, causing many engineers to be very unfamiliar with COOLMOS applications. It can be seen that COOLMOS still has a lot of Market space."

Jotrin Electronics also has related testing projects,In this field, wehave rich experience.Our testing machines can test rated breakdown voltage and also test avalanche mode .

test rated breakdown voltage and also test get into avalanche mode  

Characteristics of Cool-mos Testing output and transfer technical :

Characteristics of Cool-mos Testing output transfer technical


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