Products > Integrated Circuits (ICs) > Clock & Timer ICs > ZL30100QDG1
ZL30100QDG1 64-TQFP
  • ZL30100QDG1
  • ZL30100QDG1 0
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T1/E1 System Synchronizer

Manufacturer :
Microchip Technology, Inc
Package/Case :
Product Categories :
Clock Generators
RoHs Status:
Lead free/RoHS Compliant

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ZL30100QDG1 Product Details

The ZL30100QDG1 T1/E1 System Synchronizer contains a digital phase-locked loop (DPLL), which provides timing and synchronization for multi-trunk T1 and E1 transmission equipment.The ZL30100QDG1 generates ST-BUS and other TDM clock and framing signals that are phase locked to one of two input references. It helps ensure system reliability by monitoring its references for accuracy and stability and by maintaining stable output clocks during reference switching operations and during short periods when a reference is unavailable.The ZL30100QDG1 is intended to be the central timing and synchronization resource for network equipment that complies with Telcordia, ETSI, ITU-T and ANSI network specifications.Simplified Block DiagramTypical ApplicationsSynchronization and timing control for multi-trunk DS1/E1 systems such as DSLAMs, gateways and PBXsClock and frame pulse source for ST-BUS, GCI and other time division multiplex (TDM) busesLine Card synchronization for PDH system


  • Supports Telcordia GR-1244-CORE Stratum 4 and Stratum 4E
  • Supports ITU-T G.823 and G.824 for 2048 kbps and 1544 kbps interfaces
  • Supports ANSI T1.403 and ETSI ETS 300 011 for ISDN primary rate interfaces
  • Simple hardware control interface
  • Accepts two input references and synchronizes to any combination of 8 kHz, 1.544 MHz, 2.048 MHz, 8.192 MHz or 16.384 MHz inputs
  • Provides a range of clock outputs: 1.544 MHz, 2.048 MHz, 16.384 MHz and either 4.096 MHz and 8.192 MHz or 32.768 MHz and 65.536 MHz
  • Provides 5 styles of 8 kHz framing pulses
  • Holdover frequency accuracy of 1.5 x 10-7
  • Lock, Holdover and selectable Out of Range indication
  • Selectable loop filter bandwidth of 1.8 Hz or 922 Hz
  • Less than 0.5 nspp jitter on all output clocks
  • External master clock source: clock oscillator or crystal


  • Synchronization and timing control for multi-trunk DS1/E1 systems such as DSLAMs, gateways and PBXs
  • Clock and frame pulse source for ST-BUS, GCI and other time division multiplex (TDM) buses
  • Line Card synchronization for PDH system

ZL30100QDG1 Block Diagram
(Picture: Diagram)

Technical Parameters

PLL Yes Frequency Max 65.536MHz
Main Purpose T1/E1 Voltage Supply 2.97V ~ 3.63V
Input Clock, Crystal Operating Temperature -40??C ~ 85??C
Output Clock Mounting Type Surface Mount
Number of Circuits 1 Package / Case 64-TQFP
Ratio Input:Output 3:8 Supplier Device Package 64-TQFP (10x10)
Differential Input:Output No/No

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Microchip Technology Inc. is a leading manufacturer of microcontroller and analog products, providing low-risk product development, lower total system cost, and faster time to market for thousands of...
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