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PowerQUICC II Integrated Communications Processor

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XPC8260CZUIHB Product Details

The XPC8260CZUIHB detailed information on power considerations, DC/AC electrical characteristics, and AC timing specifications for the .29 μm (HiP3) devices of the PowerQUICC II family of communications processors: the MPC8260. Throughout this document.


The major features of the MPC8260 are as follows:

• Dual-issue integer core

— A core version of the EC603e microprocessor

— System core microprocessor supporting frequencies of 133–200 MHz (150–200 MHz for the


— Separate 16-Kbyte data and instruction caches:

– Four-way set associative

– Physically addressed

– LRU replacement algorithm

— PowerPC architecture-compliant memory management unit (MMU)

— Common on-chip processor (COP) test interface

— High-performance (4.4–5.1 SPEC95 benchmark at 200 MHz; 280 Dhrystones MIPS at

200 MHz)

— Supports bus snooping for data cache coherency

— Floating-point unit (FPU)

• Separate power supply for internal logic and for I/O

• Separate PLLs for G2 core and for the CPM

— G2 core and CPM can run at different frequencies for power/performance optimization

— Internal core/bus clock multiplier that provides 1.5:1, 2:1, 2.5:1, 3:1, 3.5:1, 4:1, 5:1, 6:1 ratios

— Internal CPM/bus clock multiplier that provides 2:1, 2.5:1, 3:1, 3.5:1, 4:1, 5:1, 6:1 ratios

• 64-bit data and 32-bit address 60x bus

— Bus supports multiple master designs

— Supports single- and four-beat burst transfers

— 64-, 32-, 16-, and 8-bit port sizes controlled by on-chip memory controller

— Supports data parity or ECC and address parity

• 32-bit data and 18-bit address local bus

— Single-master bus, supports external slaves

— Eight-beat burst transfers

— 32-, 16-, and 8-bit port sizes controlled by on-chip memory controller

• System interface unit (SIU)

— Clock synthesizer

— Reset controller

— Real-time clock (RTC) register

— Periodic interrupt timer

— Hardware bus monitor and software watchdog timer

— IEEE Std 1149.1™ JTAG test access port

• Twelve-bank memory controller

— Glueless interface to SRAM, page mode SDRAM, DRAM, EPROM, Flash and other userdefinable peripherals

— Byte write enables and selectable parity generation

— 32-bit address decodes with programmable bank size

— Three user programmable machines, general-purpose chip-select machine, and page-mode

pipeline SDRAM machine

— Byte selects for 64 bus width (60x) and byte selects for 32 bus width (local)

— Dedicated interface logic for SDRAM

• CPU core can be disabled and the device can be used in slave mode to an external core

• Communications processor module (CPM)

XPC8260CZUIHB Block Diagram
(Picture: Diagram)

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