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XC2C512-10PQ208I

512 MACROCELL 1.8V ZERO POWER ISP CPLD

  • Package/Case :
  • QFP208
  • Product Categories :
  • CPLDs (Complex Programmable Logic Devices)
  • RoHs Status:
  • Lead free/RoHS Compliant
  • Marking Code:
  • XC2C512
  • In-stock:
  • 950

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XC2C512-10PQ208I Product Details

Description 
The CoolRunner-ll 512-macrocell device is designed for both high performance and low power applications. This lends power savings to high-end communication equipment and high speed to battery operated devices. Due to the lowpower stand-by and dynamic operation, overall system reliability is improved This device consists of thirty two Function Blocks interconnected by a low power Advanced Interconnect Matrix(AlM).
The AlM feeds 40 true and complement inputs to each Function Block. The Function Blocks consist of a 40 by 56 P-tem PLA and 16 macrocells which contain numerous configuration bits that allow for combinational or registered modes of operation.
Additionally, these registers can be globally reset or preset and configured as a D or T flip-flop or as a D latch. There are also multiple clock signals, both global and local product term types, configured on a per macrocell basis. Output pin configurations include slew rate limit, bus hold, pull-up, open drain and programmable grounds.A Schmitt-trigger input is available on a per input pin basis. In addition to storing macrocell output states, the macrocell registers may be configured as "direct input"registers to store signals directly from input pins.

Features
· Optimized for 1.8V systems 
  As fast as 7.1 ns pin-to-pin delays
  As low as 14 uA quiescent current
· Industry's best 0.18 micron CMOS CPLD
  Optimized architecture for effective logic synthesis
  Multi-voltage /O operation -1.5V to 3.3V
· Available in multiple package options 
  208-pin PQFP with 173 user I/O
  256-ball FT(1.0mm) BGA with 212 user I/O
  324-ball FG(1.0mm) BGA with 270 user I/O
  Pb-free available for all packages
· Advanced system features
  Fastest in system programming
·1.8V ISP using IEEE 1532(JTAG) interface 
  IEEE1149.1 JTAG Boundary Scan Test 
  Optional Schmitt-trigger input(per pin)
  Unsurpassed low power management DataGATE enable signal control
  Four separate /O banks 
  RealDigital 100% CMOS product term generation 
  Flexible clocking modes Optional DualEDGE triggered registers Ciock divider(divide by 2,4,6,8,10,12,14,16)
  CoolCLOCK
  Global signal options with macrocell control 
  Multiple global clocks with phase selection per macrocell 
  Multiple global output enables Global set/reset
  Advanced design security 
  PLA architecture 
  Superior pinout retention
  100% product term routability across function block
  Open-drain output option for Wired-OR and LED drive 
  Optional bus-hold,3-state or weak pullup on selected /O pins 
  Optional configurable grounds on unused /Os 
  Mixed I/O voltages compatible with 1.5V,1.8V,
  2.5V, and 3.3V logic levels 
  SSTL2-1, SSTL3-1, and HSTL-1/0 compatiblility 
· Hot Pluggable

XC2C512-10PQ208I

Feature

• Optimized for 1.8V systems
- As fast as 7.1 ns pin-to-pin delays
- As low as 14 μA quiescent current
• Industry’s best 0.18 micron CMOS CPLD
- Optimized architecture for effective logic synthesis
- Multi-voltage I/O operation — 1.5V to 3.3V
• Available in multiple package options
- 208-pin PQFP with 173 user I/O
- 256-ball FT (1.0mm) BGA with 212 user I/O
- 324-ball FG (1.0mm) BGA with 270 user I/O
- Pb-free available for all packages
• Advanced system features
- Fastest in system programming
· 1.8V ISP using IEEE 1532 (JTAG) interface
- IEEE1149.1 JTAG Boundary Scan Test
- Optional Schmitt-trigger input (per pin)
- Unsurpassed low power management
· DataGATE enable signal control
- Four separate I/O banks
- RealDigital 100% CMOS product term generation
- Flexible clocking modes
· Optional DualEDGE triggered registers
· Clock divider (divide by 2,4,6,8,10,12,14,16)
· CoolCLOCK
- Global signal options with macrocell control
· Multiple global clocks with phase selection per
macrocell
· Multiple global output enables
· Global set/reset
- Advanced design security
- PLA architecture
· Superior pinout retention
· 100% product term routability across function block
- Open-drain output option for Wired-OR and LED drive
- Optional bus-hold, 3-state or weak pullup on selected I/O pins
- Optional configurable grounds on unused I/Os
- Mixed I/O voltages compatible with 1.5V, 1.8V, 2.5V, and 3.3V logic levels
· SSTL2-1, SSTL3-1, and HSTL-1 I/O compatibility
- Hot Pluggable

XC2C512-10PQ208I Products

XC2C512-10PQ208I Pinout
(Picture: Pinout)

XC2C512-10PQ208I Block Diagram
(Picture: Diagram)

Technical Parameters

  • Programmable Type
  • In System Programmable
  • Delay Time tpd(1) Max
  • 9.2ns
  • Voltage Supply Internal
  • 1.7V ~ 1.9V
  • Number of Logic Elements/Blocks
  • 32
  • Number of Macrocells
  • 512
  • Number of Gates
  • 12000
  • Number of I/O
  • 173
  • Operating Temperature
  • -40??C ~ 85??C (TA)
  • Mounting Type
  • Surface Mount
  • Package / Case
  • 208-BFQFP
  • Supplier Device Package
  • 208-PQFP (28x28)

XC2C512-10PQ208I Documents

  • XC2C512 Technical Support PDF Datasheet Overview

XC2C512-10PQ208I Related Products

Ratings and Reviews (1)

  • 5 / 5
  • 5 Stars 100%
  • 4 Stars 0%
  • 3 Stars 0%
  • 2 Stars 0%
  • 1 Stars 0%
  • **enis***
    2020-03-28

    Part well packaged! Excellent in working condition.

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Q: How does Jotrin guarantee that XC2C512-10PQ208I is the original manufacturer or agent of XILINX?
We have a professional business development department to strictly test and verify the qualifications of XILINX original manufacturers and agents. All XILINX suppliers must pass the qualification review before they can publish their XC2C512-10PQ208I devices; we pay more attention to the channels and quality of XC2C512-10PQ208I products than any other customer. We strictly implement supplier audits, so you can purchase with confidence.
Q: How to find the detailed information of XC2C512-10PQ208I chips? Including XILINX original factory information, CPLDs (Complex Programmable Logic Devices) application, XC2C512-10PQ208I pictures?
You can use Jotrin's intelligent search engine, or filter by CoolRunner-II CPLD category, or find it through Xilinx, Inc Information page.
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All goods will implement Pre-Shipment Inspection (PSI), selected at random from all batches of your order to do a systematic inspection before arranging the shipment. If there is something wrong with the XC2C51210PQ208I we delivered, we will accept the replacement or return of the XC2C512-10PQ208I only when all of the below conditions are fulfilled:
(1)Such as a deficiency in quantity, delivery of wrong items, and apparent external defects (breakage and rust, etc.), and we acknowledge such problems.
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Xilinx, Inc

Xilinx
Xilinx is the inventor of the FPGA, CPLDs, programmable SoCs, and now, the ACAP, their highly-flexible programmable silicon, enabled by a suite of advanced software and tools, drives rapid innovation across a wide span of industries and technologies - from consumer to cars to the cloud....

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