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CPLD CoolRunner -II Family 12K Gates 512 Macro Cells 128MHz 0.18um (CMOS) Technology 1.8V
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XC2C512-10FGG324C Product Details
The CoolRunner-II 512-macrocell device is designed for both high performance and low power applications. This lends power savings to high-end communication equipment and high speed to battery operated devices. Due to the low power stand-by and dynamic operation, overall system reliability is improved This device consists of thirty two Function Blocks inter-connected by a low power Advanced Interconnect Matrix (AIM). The AIM feeds 40 true and complement inputs to each Function Block. The Function Blocks consist of a 40 by 56 P-term PLA and 16 macrocells which contain numerous configuration bits that allow for combinational or registered modes of operation. Additionally, these registers can be globally reset or preset and configured as a D or T flip-flop or as a D latch. There are also multiple clock signals, both global and local product term types, configured on a per macrocell basis. Output pin configurations include slew rate limit, bus hold, pull-up, open drain and programmable grounds.
A Schmitt-trigger input is available on a per input pin basis. In addition to storing macrocell output states, the macrocell registers may be configured as "direct input" registers to store signals directly from input pins. Clocking is available on a global or Function Block basis. Three global clocks are available for all Function Blocks as a synchronous clock source. Macrocell registers can be individually configured to power up to the zero or one state. A global set/reset control line is also available to asynchronously set or reset selected registers during operation. Additional local clock, synchronous clock-enable, asynchronous set/reset and output enable signals can be formed using product terms on a per-macrocell or per-Function Block basis. A DualEDGE flip-flop feature is also available on a per macrocell basis. This feature allows high performance synchronous operation based on lower frequency clocking to help reduce the total power consumption of the device. Circuitry has also been included to divide one externally supplied global clock (GCK2) by eight different selections. This yields divide by even and odd clock frequencies.
- As fast as 7.1 ns pin-to-pin delays
- As low as 14 μA quiescent current
• Industry’s best 0.18 micron CMOS CPLD
- Optimized architecture for effective logic synthesis
- Multi-voltage I/O operation — 1.5V to 3.3V
• Available in multiple package options
- 208-pin PQFP with 173 user I/O
- 256-ball FT (1.0mm) BGA with 212 user I/O
- 324-ball FG (1.0mm) BGA with 270 user I/O
- Pb-free available for all packages
• Advanced system features
- Fastest in system programming
· 1.8V ISP using IEEE 1532 (JTAG) interface
- IEEE1149.1 JTAG Boundary Scan Test
- Optional Schmitt-trigger input (per pin)
- Unsurpassed low power management
· DataGATE enable signal control
- Four separate I/O banks
- RealDigital 100% CMOS product term generation
- Flexible clocking modes
· Optional DualEDGE triggered registers
· Clock divider (divide by 2,4,6,8,10,12,14,16)
- Global signal options with macrocell control
· Multiple global clocks with phase selection per
· Multiple global output enables
· Global set/reset
- Advanced design security
- PLA architecture
· Superior pinout retention
· 100% product term routability across function block
- Open-drain output option for Wired-OR and LED drive
- Optional bus-hold, 3-state or weak pullup on selected I/O pins
- Optional configurable grounds on unused I/Os
- Mixed I/O voltages compatible with 1.5V, 1.8V, 2.5V, and 3.3V logic levels
· SSTL2-1, SSTL3-1, and HSTL-1 I/O compatibility
- Hot Pluggable
- Programmable Type
- In System Programmable
- Delay Time tpd(1) Max
- Voltage Supply Internal
- 1.7V ~ 1.9V
- Number of Logic Elements/Blocks
- Number of Macrocells
- Number of Gates
- Number of I/O
- Operating Temperature
- 0??C ~ 70??C (TA)
- Mounting Type
- Surface Mount
- Package / Case
- Supplier Device Package
- 324-FBGA (23x23)
XC2C512 Technical Support PDF Datasheet Overview
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Estimated Delivery Time: Sep 24 - Sep 29 days (choose Expedited at checkout).
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1.We provide 90 days warranty.
2.If some of the items you received aren't of perfect quality, we would resiponsibly arrange your refund or replacement. But the items must remain their orginal condition.
- Q: How does Jotrin guarantee that XC2C512-10FGG324C is the original manufacturer or agent of XILINX?
- We have a professional business development department to strictly test and verify the qualifications of XILINX original manufacturers and agents. All XILINX suppliers must pass the qualification review before they can publish their XC2C512-10FGG324C devices; we pay more attention to the channels and quality of XC2C512-10FGG324C products than any other customer. We strictly implement supplier audits, so you can purchase with confidence.
- Q: How to find the detailed information of XC2C512-10FGG324C chips? Including XILINX original factory information, Embedded - CPLDs (Complex Programmable Logic Devices) application, XC2C512-10FGG324C pictures?
- You can use Jotrin's intelligent search engine, or filter by CoolRunner-II CPLD category, or find it through Xilinx, Inc Information page.
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- The XILINX's inventory fluctuates greatly and cannot be updated in time, it will be updated periodically within 24 hours. After submitting an order for XC2C512-10FGG324C, it is recommended to confirm the order with Jotrin salesperson or online customer service before payment.
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- Q: What is the process for returns or replacement of XC2C512-10FGG324C?
All goods will implement Pre-Shipment Inspection (PSI), selected at random from all batches of your order to do a systematic inspection before arranging the shipment.
If there is something wrong with the XC2C51210FGG324C we delivered, we will accept the replacement or return of the XC2C512-10FGG324C only when all of the below conditions are fulfilled:
(1)Such as a deficiency in quantity, delivery of wrong items, and apparent external defects (breakage and rust, etc.), and we acknowledge such problems.
(2)We are informed of the defect described above within 90 days after the delivery of XC2C512-10FGG324C.
(3)The XC2C512-10FGG324C is unused and only in the original unpacked packaging.
Two processes to return the products:
(1)Inform us within 90 days
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More details about return electronic components please see our Return & Change Policy.
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- 3.Xilinx-FPGA DNA reading method
- 4.Xilinx-7Series-FPGA high-speed transceiver use learning
- 5.FPGAs, 3D ICs, and MPSoCs suit LTE Advanced applications
- 6.Development Environment supports SoCs and MPSoCs.
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