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XC2C32A-6VQG44I

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32 MACROCELL 1.8V ZERO POWER ISP CPLD

Manufacturer : AMD Xilinx, Inc
Package/Case : TQFP44
Product Categories : CPLDs
Datasheet: XC2C32A-6VQG44I Datasheet (PDF)
RoHs Status: Lead free/RoHS Compliant
In-stock: 6000

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XC2C32A-6VQG44I Product Details

The CoolRunner-II 128-macrocell device is designed for both high performance and low power applications. This lends power savings to high-end communication equipment and high speed to battery operated devices. Due to the low power stand-by and dynamic operation, overall system reliability is improved

This device consists of eight Function Blocks inter-connected by a low power Advanced Interconnect Matrix (AIM). The AIM feeds 40 true and complement inputs to each Function Block. The Function Blocks consist of a 40 by 56 P-term PLA and 16 macrocells which contain numerous configuration bits that allow for combinational or registered modes of operation.

Additionally, these registers can be globally reset or preset and configured as a D or T flip-flop or as a D latch. There are also multiple clock signals, both global and local product term types, configured on a per macrocell basis. Output pin configurations include slew rate limit, bus hold, pull-up, open drain and programmable grounds. A Schmitt-trigger input is available on a per input pin basis. In addition to storing macrocell output states, the macrocell registers may be configured as direct input registers to store signals directly from input pins.

Clocking is available on a global or Function Block basis. Three global clocks are available for all Function Blocks as a synchronous clock source. Macrocell registers can be individually configured to power up to the zero or one state. A global set/reset control line is also available to asynchronously set or reset selected registers during operation. Additional local clock, synchronous clock-enable, asynchronous set/reset and output enable signals can be formed using product terms on a per-macrocell or per-Function Block basis.

A DualEDGE flip-flop feature is also available on a per macrocell basis. This feature allows high performance synchronous operation based on lower frequency clocking to help reduce the total power consumption of the device.

Circuitry has also been included to divide one externally supplied global clock (GCK2) by eight different selections. This yields divide by even and odd clock frequencies.

The use of the clock divide (division by 2) and DualEDGE flip-flop gives the resultant CoolCLOCK feature

DataGATE is a method to selectively disable inputs of the CPLD that are not of interest during certain points in time.

By mapping a signal to the DataGATE function, lower power can be achieved due to reduction in signal switching.

Another feature that eases voltage translation is I/O banking. Two I/O banks are available on the CoolRunner-II 128 macrocell device that permit easy interfacing to 3.3V, 2.5V, 1.8V, and 1.5V devices.

The CoolRunner-II 128 macrocell CPLD is I/O compatible with various JEDEC I/O standards (see Table 1). This device is also 1.5V I/O compatible with the use of Schmitt-trigger inputs.

Table 1: I/O Standards for XC2C128(1)

IOSTANDARD AttributeOutput VCCIOInput VCCIOInput VREFBoard Termination Voltage VTTLVTTL3.33.3N/AN/ALVCMOS333.33.3N/AN/ALVCMOS252.52.5N/AN/ALVCMOS181.81.8N/AN/ALVCMOS15(2)1.51.5N/AN/AHSTL_11.51.50.750.75SSTL2_12.52.51.251.25SSTL3_13.33.31.51.5

XC2C32A-6VQG44I

Feature

• In-System Programmable PROMs for Configuration of Xilinx® FPGAs

• Low-Power Advanced CMOS NOR Flash Process

• Endurance of 20,000 Program/Erase Cycles

• Operation over Full Industrial Temperature Range (–40°C to +85°C)

• IEEE Standard 1149.1/1532 Boundary-Scan (JTAG) Support for Programming, Prototyping, and Testing

• JTAG Command Initiation of Standard FPGA Configuration

Technical Parameters

  • Programmable Type
  • In System Programmable
  • Delay Time tpd(1) Max
  • 5.5ns
  • Voltage Supply Internal
  • 1.7V ~ 1.9V
  • Number of Logic Elements/Blocks
  • 2
  • Number of Macrocells
  • 32
  • Number of Gates
  • 750
  • Number of I/O
  • 33
  • Operating Temperature
  • -40??C ~ 85??C (TA)
  • Mounting Type
  • Surface Mount
  • Package / Case
  • 44-TQFP
  • Supplier Device Package
  • 44-VQFP (10x10)

XC2C32A-6VQG44I Datasheet

  • XC2C32A Technical Support PDF Datasheet Overview

XC2C32A-6VQG44I Related Products

Ratings and Reviews (1)

  • 5 / 5
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  • 4 Stars 0%
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  • 1 Stars 0%
  • **an P***
    2020-03-12

    Good price, packed safe, shipped fast. A+++++

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1.The electronic components you purchase include 365 Days Warranty, We guarantee product quality.

2.If some of the items you received aren't of perfect quality, we would resiponsibly arrange your refund or replacement. But the items must remain their orginal condition.

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Q: How does Jotrin guarantee that XC2C32A-6VQG44I is the original manufacturer or agent of XILINX?
We have a professional business development department to strictly test and verify the qualifications of XILINX original manufacturers and agents. All XILINX suppliers must pass the qualification review before they can publish their XC2C32A-6VQG44I devices; we pay more attention to the channels and quality of XC2C32A-6VQG44I products than any other customer. We strictly implement supplier audits, so you can purchase with confidence.
Q: How to find the detailed information of XC2C32A-6VQG44I chips? Including XILINX original factory information, CPLDs application, XC2C32A-6VQG44I pictures?
You can use Jotrin's intelligent search engine, or filter by CoolRunner-II CPLD category, or find it through AMD Xilinx, Inc Information page.
Q: Are the XILINX's XC2C32A-6VQG44I price and stock displayed on the platform accurate?
The XILINX's inventory fluctuates greatly and cannot be updated in time, it will be updated periodically within 24 hours. After submitting an order for XC2C32A-6VQG44I, it is recommended to confirm the order with Jotrin salesperson or online customer service before payment.
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Note: It may take up to 24 hours before carriers will display tracking information. In normal conditions, Express delivery needs 3-5 days, Registered Mail needs 25-60 days.
Q: What is the process for returns or replacement of XC2C32A-6VQG44I?
All goods will implement Pre-Shipment Inspection (PSI), selected at random from all batches of your order to do a systematic inspection before arranging the shipment. If there is something wrong with the XC2C32A6VQG44I we delivered, we will accept the replacement or return of the XC2C32A-6VQG44I only when all of the below conditions are fulfilled:
(1)Such as a deficiency in quantity, delivery of wrong items, and apparent external defects (breakage and rust, etc.), and we acknowledge such problems.
(2)We are informed of the defect described above within 90 days after the delivery of XC2C32A-6VQG44I.
(3)The XC2C32A-6VQG44I is unused and only in the original unpacked packaging.
Two processes to return the products:
(1)Inform us within 90 days
(2)Obtain Requesting Return Authorizations
More details about return electronic components please see our Return & Change Policy.
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AMD Xilinx, Inc

Xilinx
Xilinx is the inventor of the FPGA, CPLDs, programmable SoCs, and now, the ACAP, their highly-flexible programmable silicon, enabled by a suite of advanced software and tools, drives rapid innovation across a wide span of industries and technologies - from consumer to cars to the cloud....

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