XC2064-100PC68C Product Details
The Logic Cell Array (LCA) is a high density CMOS integrated circuit. Its user-programmable array architec-ture is made up of three types of configurable elements: Input/Output Blocks, logic blocks and Interconnect. The designer can define individual l/O blocks for interface to external circuitry, define logic blocks to implement logic functions and define interconnection networks to compose larger scale logic functions. The XACT Development System provides interactive graphic design capture and auto-matic routing. Both logic simulation and in-circuit emula-tion are available for design verification.
The XC2000 family operates with a nominal 5.0 V supply.
The XC2000L family operates with nominal 3.3 V supply.
The LCA logic functions and interconnections are determined by data stored in internal static-memory cells. On-chip logic provides for automatic loading of configuration data at power-up. The program data can reside in an EEPROM, EPROM or ROM on the circuit board or on a floppy disk or hard disk. The program can be loaded in a number of modes to accommodate various system requirements.
The general structure of a Logic Cell Array is shown in Figure 1. The elements of the array include three catego-
ries of user programmable elements:I/O Blocks(IOBs), Configurable Logic Blocks (CLBs) and Programmable Interconnections. The I/OBs provide an interface between the logic array and the device package pins. The CLBs perform user-specified logic functions, and the interconnect resources are programmed to form networks that carry logic signals among the blocks.
LCA configuration is established through a distributed array of memory cells. The XACT development system generates the program used to configure the Logic CellArray which includes logic to implement automatic con-
The configuration of the Logic Cell Array is established by programming memory cells which determine the logic functions and interconnections. The memory loading process is independent of the user logic functions.
-Digital logic functions
· General-purpose array architecture
· Complete user control of design cycle
· Compatible arrays with logic cell complexity equivalent from 600 to 1,500 gates
· Available in 5-V and 3.3-V versions
·100% factory tested
· Selectable configuration modes
· Low-power, CMOS, static-memory technology
· Performance equivalent to TTL SSI/MSI
· TTL or CMOS input thresholds
· Complete development system support
-XACT Design Editor
-Logic and Timing Simulator
- Tape & Reel (TR)/Cut Tape (CT)/Tray/Tube
- RoHs Status
- Lead free/RoHS Compliant
XC2000 Logic Cell Array Families Datasheet
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1.We provide 90 days warranty.
2.If some of the items you received aren't of perfect quality, we would resiponsibly arrange your refund or replacement. But the items must remain their orginal condition.
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All goods will implement Pre-Shipment Inspection (PSI), selected at random from all batches of your order to do a systematic inspection before arranging the shipment.
If there is something wrong with the XC2064100PC68C we delivered, we will accept the replacement or return of the XC2064-100PC68C only when all of the below conditions are fulfilled:
(1)Such as a deficiency in quantity, delivery of wrong items, and apparent external defects (breakage and rust, etc.), and we acknowledge such problems.
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(3)The XC2064-100PC68C is unused and only in the original unpacked packaging.
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