XA7Z030-1FBV484Q Product Details
The XA Zynq-7000 family offers the flexibility and scalability of an FPGA, while providing the performance, power, and ease of use typically associated with ASICs and ASSPs. The range of devices in the XA Zynq-7000 SoC family allows designers to target cost-sensitive as well as high-performance applications from a single platform using industry-standard tools. While each device in the XA Zynq-7000 family contains the same PS, the PL and I/O resources vary between the devices.
The XA Zynq-7000 architecture enables implementation of custom logic in the PL and custom software in the PS. It allows for the realization of unique and differentiated system functions. The integration of the PS with the PL allows levels of performance that two-chip solutions (e.g., an ASSP with an FPGA) cannot match due to their limited I/O bandwidth, latency, and power budgets.
Xilinx offers a large number of soft IP for the XA Zynq-7000 family. Stand-alone and Linux device drivers are available for the peripherals in the PS and the PL. The award-winning ISE® Design Suite: System Edition development environment enables a rapid product development for software, hardware, and systems engineers. Adoption of the ARM-based PS also brings a broad range of third-party tools and IP providers in combination with Xilinx’s existing PL ecosystem. The inclusion of an application processor enables high-level operating system support, e.g., Linux. Other standard operating systems used with the Cortex-A9 processor are also available for the XA Zynq-7000 family. The PS and the PL are on separate power domains, enabling the user of these devices to power down the PL for power management if required. The processors in the PS always boot first, allowing a software centric approach for PL configuration. PL configuration is managed by software running on the CPU, so it boots similar to an ASSP.
The XA Zynq™-7000 Automotive family is based on the Xilinx® All Programmable SoC architecture. These products integrate a feature-rich dual-core ARM® Cortex™-A9 based processing system (PS) and 28 nm Xilinx programmable logic (PL) in a single device. The ARM Cortex-A9 CPUs are the heart of the PS and also include on-chip memory, external memory interfaces, and a rich set of peripheral connectivity interfaces. This highly integrated, flexible, and power-optimized solution is ideal for high computationally intensive and performance demanding applications. The automotive family focuses on automotive applications and consists of the Z-7010, Z-7020, and Z-7030 devices.
- 2.5 DMIPS/MHz per CPU
- CPU frequency: Up to 667 MHz
- Coherent multiprocessor support
- ARMv7-A architecture
- TrustZone security
- Thumb-2 instruction set
- Jazelle RCT execution Environment Architecture
- NEON media-processing engine
- Single and double precision Vector Floating Point Unit (VFPU)
- CoreSight™ technology and Program Trace Macrocell (PTM)
- Timer and Interrupts
- Three watchdog timers
- One global timer
- Two triple-timer counters
- 32 KB Level 1 4-way set-associative instruction and data caches (independent for each CPU)
- 512 KB 8-way set-associative Level 2 cache (shared between the CPUs)
- Byte-parity support
- On-Chip Memory
- On-chip boot ROM
- 256 KB on-chip RAM (OCM)
- Byte-parity support
- External Memory Interfaces
- Multiprotocol dynamic memory controller
- 16-bit or 32-bit interfaces to DDR3L, DDR3, DDR2, or LPDDR2 memories
- ECC support in 16-bit mode
- 1 GB of address space using single rank of 8-, 16-, or 32-bit-wide memories
- Static memory interfaces
- 8-bit SRAM data bus with up to 64 MB support
- Parallel NOR flash support
- ONFI1.0 NAND flash support (1-bit ECC)
- 1-bit SPI, 2-bit SPI, 4-bit SPI (quad-SPI), or two quad-SPI (8-bit) serial NOR flash
- 8-Channel DMA Controller
- Memory-to-memory, memory-to-peripheral, peripheral-to-memory, and scatter-gather transaction support
- I/O Peripherals and Interfaces
- Two 10/100/1000 tri-speed Ethernet MAC peripherals with IEEE Std 802.3 and IEEE Std 1588 revision 2.0 support
- Scatter-gather DMA capability
- Recognition of 1588 rev. 2 PTP frames
- GMII and RGMII interfaces
- Two USB 2.0 OTG peripherals, each supporting up to 12 Endpoints
- USB 2.0 compliant device IP core
- On-the-go, high-speed, full-speed, and low-speed modes support
- Intel EHCI compliant USB host
- 8-bit ULPI external PHY interface
- Two full CAN 2.0B compliant CAN bus interfaces
- CAN 2.0-A and CAN 2.0-B and ISO 118981-1 standard compliant
- External PHY interface
- Two SD/SDIO 2.0/MMC3.31 compliant controllers
- Two full-duplex SPI ports with three peripheral chip selects
- Two high-speed UARTs (up to 1 Mb/s)
- Two master and slave I2C interfaces
- GPIO with four 32-bit banks, of which up to 54 bits can be used with the PS I/O (one bank of 32b and one bank of 22b) and up to 64 bits (up to two banks of 32b) connected to the programmable logic (PL)
- Up to 54 flexible multiplexed I/O (MIO) for peripheral pin assignments
- High-bandwidth connectivity within PS and between PS and PL
- ARM AMBA AXI based
- QoS support on critical masters for latency and bandwidth control
- Programmable Logic (PL)
- Configurable Logic Blocks (CLB)
- Look-up tables (LUT)
- Cascadeable adders
- 36 Kb Block RAM
- True Dual-Port
- Up to 72 bits wide
- Configurable as dual 18 kb
- DSP Blocks
- 18 x 25 signed multiply
- 48-bit adder/accumulator
- 25-bit pre-adder
- Programmable I/O Blocks
- Supports LVCMOS, LVDS, and SSTL
- 1.2V to 3.3V I/O
- Programmable I/O delay and SerDes
- JTAG Boundary-Scan
- IEEE Std 1149.1 Compatible Test Interface
- Two 12-Bit Analog-to-Digital Converters
- On-chip voltage and temperature sensing
- Up to 17 external differential input channels
- One million samples per second maximum conversion rate
- Automotive Temperature Range
- I-Grade: Tj = –40°C to +100°C
- Q-Grade: Tj = –40°C to +125°C
- Automotive Standards
- AEC-Q100 qualification (Beyond AEC-Q100 Qualification is available upon request)
- Production Part Approval Process (PPAP) Documentation
- Serial Transceivers
- Up to 4 receivers and transmitters
- Supports up to 6.6 Gb/s data rates
- PCI Express® Block
- Root Complex and Endpoint configurations
- Supports up to Gen2 speeds
- Supports up to 4 lanes
- MCU, FPGA
- Core Processor
- Dual ARM? Cortex?-A9 MPCore? with CoreSight?
- RAM Size
- CANbus, EBI/EMI, Ethernet, I2C, MMC/SD/SDIO, SPI, UART/USART, USB OTG
- Primary Attributes
- Kintex?-7 FPGA, 125K Logic Cells
- Operating Temperature
- -40??C ~ 125??C (TJ)
- Package / Case
- 484-BBGA, FCBGA
- Supplier Device Package
- 484-FCBGA (23x23)
XA Zynq-7000 SoC Data Sheet: Overview
XA7Z030-1FBV484Q Related Products
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- 6.Development Environment supports SoCs and MPSoCs.
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