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1394 Interface IC 3-Port Cable Xcvr Arbiter
| Manufacturer : | TI |
|---|---|
| Package/Case : | BGA-168 |
| Product Categories : | 1394 Interface IC |
| Datasheet: | TSB81BA3EIZAJ Datasheet (PDF) |
| RoHs Status: | Rohs |
| Marking Code: | TSB81BA3EI |
| In-stock: | 0 |
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TSB81BA3EIZAJ Product Details
The TSB81BA3EIZAJ provides the digital and analog transceiver functions needed to implement a three-port node in a cable-based IEEE 1394 network. Each cable port incorporates two differential line transceivers. The transceivers include circuitry to monitor the line conditions as needed for determining connection status, for initialization and arbitration, and for packet reception and transmission. The TSB81BA3EIZAJ is designed to interface with a link-layer controller (LLC), such as the TSB82AA2, TSB12LV21, TSB12LV26, TSB12LV32, TSB42AA4, TSB42AB4, TSB12LV01B, or TSB12LV01C. It also may be connected cable port to cable port to an integrated 1394 Link + PHY layer such as the TSB43AB2.
The TSB81BA3EIZAJ can be powered by a single 3.3-V supply when the VREG_PD terminal (terminal 73 on the PFP package and terminal B7 on the ZAJ package) is tied to GND. VREG_PD enables the internal 3.3-V to 1.95-V regulator which provides the 1.95-V to the core. The When VREG_PD is pulled high to VDD through at least a 1-kΩ resistor the TSB81BA3EIZAJ internal regulator is off and the device can be powered by two separate external regulated supplies: 3.3-V for the I/Os and 1.95-V for the core. The core voltage is supplied to the PLLVDD-CORE and DVDD-CORE terminals to the requirements in the recommended operating conditions (1.95-V nominal). The PLLVDD-CORE terminals must be separated from the DVDD-CORE terminals. The PLLVDD-CORE and the DVDD-CORE terminals must be decoupled with 1 uF capacitors to stabilze the respective supply. Additional 0.10 μF and 0.01 μF high-frequency bypass capacitors may also be used. The separation between DVDD-CORE and PLLVDD-CORE may be implemented by separate power supply rails, or by a single power supply rail, where the DVDD-CORE and PLLVDD-CORE are separated by a filter network to keep noise from the PLLVDD-CORE supply.
The TSB81BA3EIZAJ requires an external 98.304-MHz crystal oscillator to generate a reference clock. The external clock drives an internal phase-locked loop (PLL), which generates the required reference signal. This reference signal provides the clock signals that control transmission of the outbound encoded information. A 49.152-MHz clock signal is supplied to the associated LLC for synchronization of the two devices and is used for resynchronization of the received data when operating the PHY-link interface in compliance with the IEEE 1394a-2000 standard. A 98.304-MHz clock signal is supplied to the associated LLC for synchronization of the two devices when operating the PHY-link interface in compliance with the IEEE P1394b standard. The power down (PD) function, when enabled by asserting the PD terminal high, stops operation of the PLL.
Feature
- Fully Supports Provisions of IEEE P1394b Revision 1.33+ at 1-Gigabit Signaling Rates
- Fully Supports Provisions of IEEE 1394a-2000 and 1394-1995 Standard for High Performance Serial Bus
- Fully Interoperable With Firewire, i.LINK, and SB1394?, Implementation of IEEE Std 1394
- Provides Three Fully Backward Compatible, (1394a-2000 Fully Compliant) Bilingual P1394b Cable Ports at up to 800 Megabits per Second (Mbits/s)
- Provides Three 1394a-2000 Fully Compliant Cable Ports at 100/200/400 Mbits/s
- Full 1394a-2000 Support Includes:
- Connection Debounce
- Arbitrated Short Reset
- Multispeed Concatenation
- Arbitration Acceleration
- Fly-By Concatenation
- Port Disable/Suspend/Resume
- Extended Resume Signaling for Compatibility With Legacy DV Devices
- Power-Down to Conserve Energy in Battery Powered Applications
- Low-Power Sleep Mode
- Fully Compliant With Open Host Controller Interface (HCI) Requirements
- Cable Power Presence Monitoring
- Cable Ports Monitor Line Conditions for Active Connection to Remote Node
- Register Bits Give Software Control of Contender Bit, Power Class Bits, Link Active Control Bit, and 1394a-2000
- Data Interface to Link-Layer Controller Pin Selectable From 1394a-2000 Mode (2/4/8 Parallel Bits at 49.152 MHz) or 1394b Mode (8 Parallel Bits at 98.304 MHz)
- Interface to Link-Layer Controller Supports Low Cost TI Bus-Holder Isolation
- Interoperable With Link-Layer Controllers Using 3.3-V Supplies
- Interoperable With Other 1394 Physical Layers (PHYs) Using 1.8-V, 3.3-V, and 5-V Supplies
- Low Jitter, External Crystal Oscillator Provides Transmit and Receive Data at 100/200/400/800 Mbits/s, and Link-Layer Controller Clock at 49.152 MHz and 98.304MHz
- Separate Bias (TPBIAS) for Each Port
- Low Cost, High Performance 80-Pin TQFP (PFP) Thermally Enhanced Package and 168-Pin ZAJ (BGA) Package
- Software Device Reset (SWR)
- Fail-Safe Circuitry Senses Sudden Loss of Power to the Device and Disables the Ports to Ensure That the TSB81BA3E Does Not Load the TPBIAS of Any Connected Device and Blocks any Leakage From the Port Back to Power Plane
- The TSB81BA3E Has a 1394a-2000 Compliant Common-Mode Noise Filter on the Incoming Bias Detect Circuit to Filter Out Cross-Talk Noise
- The TSB81BA3E Is Port Programmable to Force 1394a Mode to Allow Use of 1394a Connectors (1394b Signaling Must Not Be Put Across 1394a Connectors or Cables)
- Internal Voltage Regulator Option
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(Picture: Diagram)
Technical Parameters
- Packaging
- Tray
- Factory Pack Quantity
- 260
TSB81BA3EIZAJ Datasheet
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TSB81BA3E Family Datasheet
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Guarantees
1.The electronic components you purchase include 365 Days Warranty, We guarantee product quality.
2.If some of the items you received aren't of perfect quality, we would resiponsibly arrange your refund or replacement. But the items must remain their orginal condition.
FAQ:
- Q: How does Jotrin guarantee that TSB81BA3EIZAJ is the original manufacturer or agent of TI?
- We have a professional business development department to strictly test and verify the qualifications of TI original manufacturers and agents. All TI suppliers must pass the qualification review before they can publish their TSB81BA3EIZAJ devices; we pay more attention to the channels and quality of TSB81BA3EIZAJ products than any other customer. We strictly implement supplier audits, so you can purchase with confidence.
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- You can use Jotrin's intelligent search engine, or filter by Semiconductors ; Interface ; Other interfaces category, or find it through TI brand manufacturer page.
- Q: Are the TI's TSB81BA3EIZAJ price and stock displayed on the platform accurate?
- The TI's inventory fluctuates greatly and cannot be updated in time, it will be updated periodically within 24 hours. After submitting an order for TSB81BA3EIZAJ, it is recommended to confirm the order with Jotrin salesperson or online customer service before payment.
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Note: It may take up to 24 hours before carriers will display tracking information. In normal conditions, Express delivery needs 3-5 days, Registered Mail needs 25-60 days. - Q: What is the process for returns or replacement of TSB81BA3EIZAJ?
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All goods will implement Pre-Shipment Inspection (PSI), selected at random from all batches of your order to do a systematic inspection before arranging the shipment.
If there is something wrong with the TSB81BA3EIZAJ we delivered, we will accept the replacement or return of the TSB81BA3EIZAJ only when all of the below conditions are fulfilled:
(1)Such as a deficiency in quantity, delivery of wrong items, and apparent external defects (breakage and rust, etc.), and we acknowledge such problems.
(2)We are informed of the defect described above within 90 days after the delivery of TSB81BA3EIZAJ.
(3)The TSB81BA3EIZAJ is unused and only in the original unpacked packaging.
Two processes to return the products:
(1)Inform us within 90 days
(2)Obtain Requesting Return Authorizations
More details about return electronic components please see our Return & Change Policy. - Q: How to contact us and get support, such as TSB81BA3EIZAJ datasheet pdf, TSB81BA3E pin diagram?
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