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DaVinci Digital Media System-on-Chip 361-NFBGA,Digital Signal Processors & Controllers (DSP, DSC) (DSP, DSC) DaVinci Dig Media SOC

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TMS320DM6441AZWT Product Details

The TMS320DM6441AZWT (also referenced as DM6441) leverages TI's DaVincitechnology to meet the networked media encode and decode application processingneeds of next-generation embedded devices.

The DM6441 enables OEMs and ODMs to quickly bring to market devices featuringrobust operating systems support, rich user interfaces, high processingperformance, and long battery life through the maximum flexibility of a fullyintegrated mixed processor solution.

The dual-core architecture of the DM6441 provides benefits of both DSP andReduced Instruction Set Computer (RISC) technologies, incorporating ahigh-performance TMS320C64x+ DSP core and an ARM926EJ-S core.

The ARM926EJ-S is a 32-bit RISC processor core that performs 32-bit or 16-bitinstructions and processes 32-bit, 16-bit, or 8-bit data. The core usespipelining so that all parts of the processor and memory system can operatecontinuously.

The ARM core incorporates:

  • A coprocessor 15 (CP15) and protection module
  • Data and program memory management units (MMUs) with table look-aside buffers.
  • Separate 16K-byte instruction and 8K-byte data caches. Both are four-way associative with virtual index virtual tag (VIVT).

The TMS320C64x+ DSPs are the highest-performance fixed-point DSP generationin the TMS320C6000 DSP platform. It is based on an enhanced version of thesecond-generation high-performance, advanced very-long-instruction-word (VLIW)architecture developed by Texas Instruments (TI), making these DSP cores anexcellent choice for digital media applications. The C64x is a code-compatiblemember of the C6000 DSP platform. The TMS320C64x+ DSP is an enhancement of theC64x+ DSP with added functionality and an expanded instruction set.

Any reference to the C64x DSP or C64x CPU also applies, unless otherwisenoted, to the C64x+ DSP and C64x+ CPU, respectively.

With performance of up to 4104 million instructions per second (MIPS) at aclock rate of 513 MHz, the C64x+ core offers solutions to high-performance DSPprogramming challenges. The DSP core possesses the operational flexibility ofhigh-speed controllers and the numerical capability of array processors. TheC64x+ DSP core processor has 64 general-purpose registers of 32-bit word lengthand eight highly independent functional units&151;two multipliers for a32-bit result and six arithmetic logic units (ALUs). The eight functional unitsinclude instructions to accelerate the performance in video and imagingapplications. The DSP core can produce four 16-bit multiply-accumulates (MACs)per cycle for a total of 2052 million MACs per second (MMACS), or eight 8-bitMACs per cycle for a total of 4104 MMACS. For more details on the C64x+ DSP, seethe TMS320C64x/C64x+ DSP CPU and Instruction Set Reference Guide(literature number SPRU732).

The DM6441 also has application-specific hardware logic, on-chip memory, andadditional on-chip peripherals similar to the other C6000 DSP platform devices.The DM6441 core uses a two-level cache-based architecture. The Level 1 programcache (L1P) is a 256K-bit direct mapped cache and the Level 1 data cache (L1D)is a 640K-bit 2-way set-associative cache. The Level 2 memory/cache (L2)consists of an 512K-bit memory space that is shared between program and dataspace. L2 memory can be configured as mapped memory, cache, or combinations ofthe two.

The peripheral set includes: two configurable video ports; a 10/100 Mb/sEthernet MAC (EMAC) with a management data input/output (MDIO) module; aninter-integrated circuit (I2C) bus interface; one audio serial port (ASP); two64-bit general-purpose timers each configurable as two independent 32-bittimers; one 64-bit watchdog timer; up to 71 pins of general-purpose input/output(GPIO) with programmable interrupt/event generation modes, multiplexed withother peripherals; three UARTs with hardware handshaking support on one UART;three pulse width modulator (PWM) peripherals; and two external memoryinterfaces: an asynchronous external memory interface (EMIFA) for slowermemories/peripherals, and a higher speed synchronous memory interface forDDR2.

The DM6441 device includes a video processing subsystem (VPSS) with twoconfigurable video/imaging peripherals: one video processing front-end (VPFE)input used for video capture, one video processing back-end (VPBE) output withimaging coprocessor (VICP) used for display.

The video processing front-end (VPFE) consists of a CCD controller (CCDC), apreview engine (previewer), histogram module, auto-exposure/white balance/focusmodule (H3A), and resizer. The CCDC is capable of interfacing to common videodecoders, CMOS sensors, and charge coupled devices (CCDs). The previewer is areal-time image processing engine that takes raw imager data from a CMOS sensoror CCD and converts from an RGB Bayer pattern to YUV4:2:2. The histogram and H3Amodules provide statistical information on the raw color data for use by theDM6441. The resizer accepts image data for separate horizontal and verticalresizing from 1/4x to 4x in increments of 256/N, where N is between 64 and1024.

The video processing back-end (VPBE) consists of an on-screen display engine(OSD) and a video encoder (VENC). The OSD engine is capable of handling twoseparate video windows and two separate OSD windows. Other configurationsinclude two video windows, one OSD window, and one attribute window allowing upto eight levels of alpha blending. The VENC provides four analog DACs that runat 54 MHz, providing a means for composite NTSC/PAL video, S-Video, and/orcomponent video output. The VENC also provides up to 24 bits of digital outputto interface to RGB888 devices. The digital output is capable of 8/16-bit BT.656output and/or CCIR.601 with separate horizontal and vertical syncs. VFocus (partof the VPBE functionality and operationally (e.g., 16-bit multiplexedaddress/data) is also provided.

The Ethernet media access controller (EMAC) provides an efficient interfacebetween the DM6441 and the network. The DM6441 EMAC support both 10Base-T and100Base-TX, or 10 Mbits/second (Mbps) and 100 Mbps in either half- orfull-duplex mode, with hardware flow control and quality of service (QOS)support.

The management data input/output (MDIO) module continuously polls all 32 MDIOaddresses in order to enumerate all PHY devices in the system. Once a PHYcandidate has been selected by the ARM, the MDIO module transparently monitorsits link state by reading the PHY status register. Link change events are storedin the MDIO module and can optionally interrupt the ARM, allowing the ARM topoll the link status of the device without continuously performing costly MDIOaccesses.

The HPI, I2C, SPI, USB2.0, and VLYNQ ports allow DM6441 to easily controlperipheral devices and/or communicate with host processors. The DM6441 alsoprovides Memory Stick/Memory Stick Pro card support, MMC/SD with SDIO support,and a universal serial bus (USB).

The DM6441 also includes a video/imaging coprocessor (VICP) to offload manyvideo and imaging processing tasks from the DSP core, making more DSP MIPSavailable for common video and imaging algorithms. For more information on theVICP enhanced codecs, such as H.264 and MPEG4, please contact your nearest TIsales representative.

The rich peripheral set provides the ability to control external peripheraldevices and communicate with external processors. For details on each of theperipherals, see the related sections later in this document and the associatedperipheral reference guides.

The DM6441 has a complete set of development tools for both the ARM and DSP.These include C compilers, a DSP assembly optimizer to simplify programming andscheduling, and a Windows debugger interface for visibility into source code



  • Get started today with production-ready, easy-to-use audio and video codecs for digital media processors based on DaVinci technology. Also available are various O/S Board Support Packages and software updates. All codecs are available for FREE evaluation. REQUEST FREE SOFTWARE!
  • High-Performance Digital Media SoC
    • C64x+ DSP Clock Rate
      • 405-MHz (Max) at 1.05 V or 513-MHz (Max) at 1.2 V
    • ARM926EJ-S Clock Rate
      • 202.5-MHz (Max) at 1.05 V or 256-MHz (Max) at 1.2 V
    • Eight 32-Bit C64x+ Instructions/Cycle
    • 4752 C64x+ MIPS
    • Fully Software-Compatible With C64x &153; ARM9
  • Advanced Very-Long-Instruction-Word (VLIW) TMS320C64x+ DSP Core
    • Eight Highly Independent Functional Units
      • Six ALUs (32-/40-Bit), Each Supports Single 32-Bit, Dual 16-Bit, or Quad 8-Bit Arithmetic per Clock Cycle
      • Two Multipliers Support Four 16 x 16-Bit Multiplies (32-Bit Results) per Clock Cycle or Eight 8 × 8-Bit Multiplies (16-Bit Results) per Clock Cycle
    • Load-Store Architecture With Non-Aligned Support
    • 64 32-Bit General-Purpose Registers
    • Instruction Packing Reduces Code Size
    • All Instructions Conditional
    • Additional C64x+ Enhancements
      • Protected Mode Operation
      • Exceptions Support for Error Detection and Program Redirection
      • Hardware Support for Modulo Loop Operation
  • C64x+ Instruction Set Features
    • Byte-Addressable (8-/16-/32-/64-Bit Data)
    • 8-Bit Overflow Protection
    • Bit-Field Extract, Set, Clear
    • Normalization, Saturation, Bit-Counting
    • Compact 16-Bit Instructions
    • Additional Instructions to Support Complex Multiplies
  • C64x+ L1/L2 Memory Architecture
    • 32K-Byte L1P Program RAM/Cache (Direct Mapped)
    • 80K-Byte L1D Data RAM/Cache (2-Way Set-Associative)
    • 64K-Byte L2 Unified Mapped RAM/Cache (Flexible RAM/CacheAllocation)
  • ARM926EJ-S Core
    • Support for 32-Bit and 16-Bit (Thumb Mode) Instruction Sets
    • DSP Instruction Extensions and Single Cycle MAC
    • ARM Jazelle Technology
    • Embedded ICE-RT Logic for Real-Time Debug
  • ARM9 Memory Architecture
    • 16K-Byte Instruction Cache
    • 8K-Byte Data Cache
    • 16K-Byte RAM
    • 8K-Byte ROM
  • Embedded Trace Buffer (ETB11) With 4KB Memory for ARM9 Debug
  • Endianness: Little Endian for ARM and DSP
  • Video Imaging Co-Processor (VICP)
  • Video Processing Subsystem
    • Front End Provides:
      • CCD and CMOS Imager Interface
      • BT.601/BT.656 Digital YCbCr 4:2:2 (8-/16-Bit) Interface
      • Preview Engine for Real-Time Image Processing
      • Glueless Interface to Common Video Decoders
      • Histogram Module
      • Auto-Exposure, Auto-White Balance, and Auto-Focus Module
      • Resize Engine
        • Resize Images From 1/4× to 4×
        • Separate Horizontal/Vertical Control
    • Back End Provides:
      • Hardware On-Screen Display (OSD)
      • Four 54-MHz DACs for a Combination of
        • Composite NTSC/PAL Video
        • Luma/Chroma Separate Video (S-video)
        • Component (YPbPr or RGB) Video (Progressive)
      • Digital Output
        • 8-/16-bit YUV or up to 24-Bit RGB
        • HD Resolution
        • Up to Two Video Windows
  • External Memory Interfaces (EMIFs)
    • 32-Bit DDR2 SDRAM Memory Controller With 256M-Byte Address Space (1.8-V I/O)
    • Asynchronous16-Bit Wide EMIF (EMIFA) With 128M-Byte Address Reach
      • Flash Memory Interfaces
        • NOR (8-/16-Bit-Wide Data)
        • NAND (8-/16-Bit-Wide Data)
  • Flash Card Interfaces
    • Multimedia Card (MMC)/Secure Digital (SD) with Secure Data I/O (SDIO)
    • CompactFlash Controller With True IDE Mode
    • SmartMedia
    • Memory Stick and Memory Stick Pro
  • Enhanced Direct-Memory-Access (EDMA3) Controller (64 Independent Channels)
  • Two 64-Bit General-Purpose Timers (Each Configurable as Two 32-Bit Timers)
  • One 64-Bit Watch Dog Timer
  • Three UARTs (One with RTS and CTS Flow Control)
  • One Serial Port Interface (SPI) With Two Chip-Selects
  • Master/Slave Inter-Integrated Circuit (I2C Bus)
  • Audio Serial Port (ASP)
    • I2S
    • AC97 Audio Codec Interface
    • Standard Voice Codec Interface (AIC12)
  • 10/100 Mb/s Ethernet MAC (EMAC)
    • IEEE 802.3 Compliant
    • Media Independent Interface (MII)
  • VLYNQ Interface (FPGA Interface)
  • Host Port Interface (HPI) with 16-Bit Multiplexed Address/Data
  • USB Port With Integrated 2.0 PHY
    • USB 2.0 High-/Full-Speed Client
    • USB 2.0 High-/Full-/Low-Speed Host
  • Three Pulse Width Modulator (PWM) Outputs
  • Macrovision Anticopy Protection (TMS320DM6442 only)(1)
  • On-Chip ARM ROM Bootloader (RBL) to Boot From NAND Flash or UART
  • ATA/ATAPI I/F (ATA/ATAPI-5 Specification)
  • Individual Power-Saving Modes for ARM/DSP
  • Flexible PLL Clock Generators
  • IEEE-1149.1 (JTAG) Boundary-Scan-Compatible
  • Up to 71 General-Purpose I/O (GPIO) Pins (Multiplexed With Other Device Functions)
  • 361-Pin Pb-Free BGA Package (ZWT Suffix), 0.8-mm Ball Pitch
  • 0.09-μm/6-Level Cu Metal Process (CMOS)
  • 3.3-V and 1.8-V I/O, 1.05-V or 1.2-V internal
  • Applications:
    • Digital Media
    • Networked Media Encode/Decode
    • Video Imaging
    • Portable Media Players

TMS320DM6441AZWT Block Diagram
(Picture: Diagram)

Technical Parameters

  • Core
  • TMS320
  • Data Bus Width
  • 32 bit
  • Maximum Clock Frequency
  • 513 MHz
  • Operating Supply Voltage
  • 3.15 V to 3.45 V
  • Maximum Operating Temperature
  • + 85 C
  • Package / Case
  • Mounting Style
  • Instruction Type
  • Fixed Point
  • Minimum Operating Temperature
  • 0 C
  • Processor Series
  • DaVinci DM6x
  • Product
  • DSPs
  • Series
  • TMS320DM6441
  • Factory Pack Quantity
  • 90

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