Products > Integrated Circuits (ICs) > Embedded Processors & Controllers > TMS320DM642AGNZA6
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TMS320DM642AGNZA6

Adjustable 2.5-36V +/-2.2% Tolerance, 1-100mA Shunt Regulator - PB Free; Package: TO-92 (TO-226) 5.33mm Body Height; No of Pins: 3; Container: Fan-Fold; Qty per Container: 2000,Digital Signal Processors & Controllers (DSP, DSC) (DSP, DSC) Video/Imaging Fixed-Point DSP

  • Manufacturer :
  • TI
  • Package/Case :
  • BGA-548
  • Product Categories :
  • Digital Signal Processors & Controllers (DSP, DSC)
  • RoHs Status:
  • Rohs
  • Marking Code:
  • TMS320DM642A A6 GNZ @ 2003 TI
  • In-stock:
  • 0

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TMS320DM642AGNZA6 Product Details

Features
• High-Performance Digital Media Processor
- 2-,1.67-,1.39-ns Instruction Cycle Time
- 500,600,720-MHz Clock Rate
- Eight 32-Bit Instructions/Cycle
- 4000,4800,5760 MIPS
- Fully Software-Compatible With C64xTM· VelociTl.2TM Extensions to VelociTlTM Advanced Very-Long-Instruction-Word (VLIW)    TMS320C64xTM DSP Core
- Eight Highly Independent Functional Units With VelociTl.2TM Extensions:
  · Six ALUs(32-/40-Bit), Each Supports Single 32-Bit, Dual 16-Bit, or Quad 8-Bit Arithmetic per Clock Cycle
  · Two Multipliers Support Four 16× 16-Bit Multiplies (32-Bit Results) per Clock Cycle or Eight 8 x 8-Bit Multiplies (16-Bit Results)       per Clock Cycle
- Load-Store Architecture With Non-Aligned Support
- 64 32-Bit General-Purpose Registers
- Instruction Packing Reduces Code Size
- All Instructions Conditional
• Instruction Set Features
- Byte-Addressable (8-/16-/32-/64-Bit Data)
- 8-Bit Overflow Protection
- Bit-Field Extract, Set, Clear
- Normalization, Saturation, Bit-Counting
- VelociTl.2M Increased Orthogonality
• L1/L2 Memory Architecture
- 128K-Bit(16K-Byte)L1P Program Cache (Direct Mapped)
- 128K-Bit(16K-Byte)L1D Data Cache(2-Way Set-Associative)
- 2M-Bit (256K-Byte)L2 Unified Mapped RAM/Cache(Flexible RAM/Cache Allocation)
• Endianess: Little Endian, Big Endian
• 64-Bit External Memory Interface(EMIF)
- Glueless Interface to Asynchronous Memories (SRAM and EPROM) and Synchronous Memories(SDRAM, SBSRAM, ZBT SRAM,        and FIFO)
- 1024M-Byte Total Addressable External Memory Space
• Enhanced Direct-Memory-Access(EDMA) Controller(64 Independent Channels)
• 10/100 Mb/s Ethernet MAC(EMAC)
- IEEE 802.3 Compliant
- Media Independent Interface(Mll)
- 8 Independent Transmit(TX) Channels and 1 Receive(RX) Channel
• Management Data Input/Output(MDIO)
• Three Configurable Video Ports
- Providing a Glueless I/F to Common Video Decoder and Encoder Devices
- Supports Multiple Resolutions/Video Stds
• VCXO Interpolated Control Port(VIC)
- Supports Audio/Video Synchronization· Host-Port Interface(HPI [32-/16-Bit] 
• 32-Bit/66-MHz,3.3-V Peripheral ComponentInterconnect (PCI) Master/Slave Interface Conforms to PCI Specification 2.2
• Multichannel Audio Serial Port(McASP)
- Eight Serial Data Pins
- Wide Variety of I's and Similar Bit Stream Formats
- Integrated Digital Audio I/F Transmitter Supports S/PDIF, IEC60958-1, AES-3, CP-430 Formats
• Inter-Integrated Circuit(IPC BusTM)
• Two Multichannel Buffered Serial Ports
• Three 32-Bit General-Purpose Timers
• Sixteen General-Purpose I/O(GPIO) Pins
• Flexible PLL Clock Generator
• IEEE-1149.1(JTAG) Boundary-Scan-Compatible 548-Pin Ball Grid Array(BGA) Package (GDK and ZDK Suffixes),0.8-mm Ball Pitch
• 548-Pin Ball Grid Array (BGA) Package (GNZ and ZNZ Suffixes),1.0 mm Ball Pitch
• 0.13-um/6-Level Cu Metal Process(CMOS)
• 3.3-VI/O,1.2-V Internal (-500)
• 3.3-V/O,1.4-V Internal(A-500,A-600,-600, -720)

TMS320DM642AGNZA6

Feature

  • High-Performance Digital Media Processor (TMS320DM642)
    • 2-, 1.67-, 1.39-ns Instruction Cycle Time
    • 500-, 600-, 720-MHz Clock Rate
    • Eight 32-Bit Instructions/Cycle
    • 4000, 4800, 5760 MIPS
    • Fully Software-Compatible With C64x
  • VelociTI.2 Extensions to VelociTI Advanced Very-Long-Instruction-Word VLIW) TMS320C64x DSP Core
    • Eight Highly Independent Functional Units With VelociTI.2 Extensions:
      • Six ALUs (32-/40-Bit), Each Supports Single 32-Bit, Dual 16-Bit, or Quad 8-Bit Arithmetic per Clock Cycle
      • Two Multipliers Support Four 16 x 16-Bit Multiplies (32-Bit Results) per Clock Cycle or Eight 8 x 8-Bit Multiplies (16-Bit Results) per Clock Cycle
    • Load-Store Architecture With Non-Aligned Support
    • 64 32-Bit General-Purpose Registers
    • Instruction Packing Reduces Code Size
    • All Instructions Conditional
  • Instruction Set Features
    • Byte-Addressable (8-/16-/32-/64-Bit Data)
    • 8-Bit Overflow Protection
    • Bit-Field Extract, Set, Clear
    • Normalization, Saturation, Bit-Counting
    • VelociTI.2 Increased Orthogonality
  • L1/L2 Memory Architecture
    • 128K-Bit (16K-Byte) L1P Program Cache (Direct Mapped)
    • 128K-Bit (16K-Byte) L1D Data Cache (2-Way Set-Associative)
    • 2M-Bit (256K-Byte) L2 Unified Mapped RAM/Cache (Flexible RAM/Cache Allocation)
  • Endianess: Little Endian, Big Endian
  • 64-Bit External Memory Interface (EMIF)
    • Glueless Interface to Asynchronous Memories (SRAM and EPROM) and Synchronous Memories (SDRAM, SBSRAM, ZBT SRAM, and FIFO)
    • 1024M-Byte Total Addressable External Memory Space
  • Enhanced Direct-Memory-Access (EDMA) Controller (64 Independent Channels)
  • 10/100 Mb/s Ethernet MAC (EMAC)
    • IEEE 802.3 Compliant
    • Media Independent Interface (MII)
    • 8 Independent Transmit (TX) Channels and 1 Receive (RX) Channel
  • Management Data Input/Output (MDIO)
  • Three Configurable Video Ports
    • Providing a Glueless I/F to Common Video Decoder and Encoder Devices
    • Supports Multiple Resolutions and Video Standards
  • VCXO Interpolated Control Port (VIC)
    • Supports Audio/Video Synchronization
  • Host-Port Interface (HPI) [32-/16-Bit]
  • 32-Bit/66-MHz, 3.3-V Peripheral Component Interconnect (PCI) Master/Slave Interface Conforms to PCI Specification 2.2
  • Multichannel Audio Serial Port (McASP)
    • Eight Serial Data Pins
    • Wide Variety of I2S and Similar Bit Stream Format
    • Integrated Digital Audio I/F Transmitter Supports S/PDIF, IEC60958-1, AES-3, CP-430 Formats
  • Inter-Integrated Circuit (I2C) Bus
  • Two Multichannel Buffered Serial Ports
  • Three 32-Bit General-Purpose Timers
  • Sixteen General-Purpose I/O (GPIO) Pins
  • Flexible PLL Clock Generator
  • IEEE-1149.1 (JTAG) Boundary-Scan-Compatible
  • 548-Pin Ball Grid Array (BGA) Package (GDK and ZDK Suffixes), 0.8-mm Ball Pitch
  • 548-Pin Ball Grid Array (BGA) Package (GNZ and ZNZ Suffixes), 1.0-mm Ball Pitch
  • 0.13-μm/6-Level Cu Metal Process (CMOS)
  • 3.3-V I/O, 1.2-V Internal (-500)
  • 3.3-V I/O, 1.4-V Internal (A-500, A-600, -600, -720)

TMS320DM642AGNZA6 Block Diagram
(Picture: Diagram)

Technical Parameters

  • Data Bus Width
  • 32 bit
  • Maximum Clock Frequency
  • 600 MHz
  • Number of Programmable I/Os
  • 16
  • Device Million Instructions per Second
  • 4800 MIPs
  • Operating Supply Voltage
  • 1.4 V
  • Maximum Operating Temperature
  • + 90 C
  • Package / Case
  • FCBGA-548
  • Mounting Style
  • SMD/SMT
  • Family / Core
  • TMS320
  • Instruction Type
  • Fixed Point
  • Minimum Operating Temperature
  • 0 C
  • Packaging
  • Tray
  • Product
  • DSPs
  • Program Memory Type
  • Asynchronous SRAM, Sychronous SDRAM, SBSRAM
  • Series
  • TMS320DM642
  • Factory Pack Quantity
  • 40
  • Tradename
  • DaVinci
  • Type
  • TMS320

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  • **ober***
    2020-03-28

    Alles bestens, Artikel wie beschrieben, schnelle, gut verpackte Lieferung. ++++

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    90 days quality guarantee for all products.

Packing

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After all the goods are ensure no problems afterpacking, we will packing safely and send by global express. It exhibitsexcellent puncture and tear resistance along with good seal integrity.

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Guarantees

1.We provide 90 days warranty.

2.If some of the items you received aren't of perfect quality, we would resiponsibly arrange your refund or replacement. But the items must remain their orginal condition.

FAQ:

Q: How does Jotrin guarantee that TMS320DM642AGNZA6 is the original manufacturer or agent of TI?
We have a professional business development department to strictly test and verify the qualifications of TI original manufacturers and agents. All TI suppliers must pass the qualification review before they can publish their TMS320DM642AGNZA6 devices; we pay more attention to the channels and quality of TMS320DM642AGNZA6 products than any other customer. We strictly implement supplier audits, so you can purchase with confidence.
Q: How to find the detailed information of TMS320DM642AGNZA6 chips? Including TI original factory information, Digital Signal Processors & Controllers (DSP, DSC) application, TMS320DM642AGNZA6 pictures?
You can use Jotrin's intelligent search engine, or filter by Processors ; Digital signal processors (DSP) ; Audio & media processors category, or find it through TI brand manufacturer page.
Q: Are the TI's TMS320DM642AGNZA6 price and stock displayed on the platform accurate?
The TI's inventory fluctuates greatly and cannot be updated in time, it will be updated periodically within 24 hours. After submitting an order for TMS320DM642AGNZA6, it is recommended to confirm the order with Jotrin salesperson or online customer service before payment.
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Q: What is the process for returns or replacement of TMS320DM642AGNZA6?
All goods will implement Pre-Shipment Inspection (PSI), selected at random from all batches of your order to do a systematic inspection before arranging the shipment. If there is something wrong with the TMS320DM642AGNZA6 we delivered, we will accept the replacement or return of the TMS320DM642AGNZA6 only when all of the below conditions are fulfilled:
(1)Such as a deficiency in quantity, delivery of wrong items, and apparent external defects (breakage and rust, etc.), and we acknowledge such problems.
(2)We are informed of the defect described above within 90 days after the delivery of TMS320DM642AGNZA6.
(3)The TMS320DM642AGNZA6 is unused and only in the original unpacked packaging.
Two processes to return the products:
(1)Inform us within 90 days
(2)Obtain Requesting Return Authorizations
More details about return electronic components please see our Return & Change Policy.
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