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TMS320DM640AZDK4

Video/Imaging Fixed-Point Digital Signal Processor 548-FCBGA,Digital Signal Processors & Controllers (DSP, DSC) (DSP, DSC) Video/Imaging Fixed Pt Dig Signal Proc

  • Manufacturer :
  • TI
  • Package/Case :
  • BGA-548
  • Product Categories :
  • Digital Signal Processors & Controllers (DSP, DSC)
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  • Rohs
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  • TMS320DM640A ZDK @ 2003 TI
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TMS320DM640AZDK4 Product Details

The TMS320C64x DSPs (including the TMS320DM641 and TMS320DM640AZDK4 devices) are the highest-performance fixed-point DSP generation in the TMS320C6000 DSP platform. The TMS320DM641 (DM641) and TMS320DM640AZDK4 (DM640) devices are based on the second-generation high-performance, advanced VelociTI very-long-instruction-word (VLIW) architecture (VelociTI.2) developed by Texas Instruments (TI), making these DSPs an excellent choice for digital media applications. The C64x is a code-compatible member of the C6000 DSP platform.

With performance of up to 4800 million instructions per second (MIPS) at a clock rate of 600 MHz, the DM641 device offers cost-effective solutions to high-performance DSP programming challenges.

With performance of up to 3200 million instructions per second (MIPS) at a clock rate of 400 MHz, the DM640 device offers cost-effective solutions to high-performance DSP programming challenges.

The DM641/DM640 DSP possesses the operational flexibility of high-speed controllers and the numerical capability of array processors. The C64x DSP core processor has 64 general-purpose registers of 32-bit word length and eight highly independent functional units-two multipliers for a 32-bit result and six arithmetic logic units (ALUs)-with VelociTI.2 extensions. The VelociTI.2 extensions in the eight functional units include new instructions to accelerate the performance in video and imaging applications and extend the parallelism of the VelociTI architecture. The DM641 can produce four 16-bit multiply-accumulates (MACs) per cycle for a total of 2400 million MACs per second (MMACS), or eight 8-bit MACs per cycle for a total of 4800 MMACS. The DM640 can produce four 16-bit multiply-accumulates (MACs) per cycle for a total of 1600 million MACs per second (MMACS), or eight 8-bit MACs per cycle for a total of 3200 MMACS. The DM641/DM640 DSP also has application-specific hardware logic, on-chip memory, and additional on-chip peripherals similar to the other C6000 DSP platform devices.

The DM641/DM640 uses a two-level cache-based architecture and has a powerful and diverse set of peripherals. The Level 1 program cache (L1P) is a 128-Kbit direct mapped cache and the Level 1 data cache (L1D) is a 128-Kbit 2-way set-associative cache. The Level 2 memory/cache (L2) consists of an 1-Mbit memory space that is shared between program and data space. L2 memory can be configured as mapped memory, cache, or combinations of the two. The peripheral set includes: two configurable video ports (DM641); one configurable video port (DM640); a 10/100 Mb/s Ethernet MAC (EMAC); a management data input/output (MDIO) module; a VCXO interpolated control port (VIC); one 4-bit multichannel buffered audio serial port (McASP0); an inter-integrated circuit (I2C) Bus module; two multichannel buffered serial ports (McBSPs); three 32-bit general-purpose timers; a 16-bit host-port interface (HPI16); a 8-pin general-purpose input/output port (GP0) with programmable interrupt/event generation modes; and a 32-bit glueless external memory interface (EMIFA), which is capable of interfacing to synchronous and asynchronous memories and peripherals.

The DM641 device has two single-channel 8-bit configurable video port peripherals (VP0 and VP1). The DM640 device has one single-channel 8-bit configurable video port peripheral (VP0). These video port peripherals provide a glueless interface to common video decoder and encoder devices. The DM641/DM640 video port peripherals support multiple resolutions and video standards (e. g., CCIR601 and ITU-).

These video port peripherals are configurable and can support either video capture and/or video display modes.

For more details on the Video Port peripherals, see the TMS320C64x DSP Video Port/VCXO Interpolated Control (VIC) Port Reference Guide (literature number SPRU629).

The McASP0 port supports one transmit and one receive clock zone, with fourserial data pins which can be individually allocated to any of the two zones.The serial port supports time-division multiplexing on each pin from 2 to 32time slots. The DM641/DM640 has sufficient bandwidth to support all 4 serialdata pins transmitting a 192-kHz stereo signal. Serial data in each zone may betransmitted and received on multiple serial data pins simultaneously andformatted in a multitude of variations on the Philips Inter-IC Sound(I2S) format.

In addition, the McASP0 transmitter may be programmed to output multipleS/PDIF, IEC60958, AES-3, CP-430 encoded data channels simultaneously, with asingle RAM containing the full implementation of user data and channel statusfields.

McASP0 also provides extensive error-checking and recovery features, such asthe bad clock detection circuit for each high-frequency master clock whichverifies that the master clock is within a programmed frequency range.

The VCXO interpolated control (VIC) port provides digital-to-analogconversion with resolution from 9-bits to up to 16-bits. The output of the VICis a single bit interpolated D/A output. For more details on the VIC port, seethe TMS320C64x DSP Video Port/VCXO Interpolated Control (VIC) Port ReferenceGuide (literature number SPRU629).

The ethernet media access controller (EMAC) provides an efficient interfacebetween the DM641/DM640 DSP core processor and the network. The DM641/DM640 EMACsupports both 10Base-T and 100Base-TX, or 10 Mbits/second (Mbps) and 100 Mbps ineither half- or full-duplex, with hardware flow control and quality of service(QOS) support. The DM641/DM640 EMAC makes use of a custom interface to the DSPcore that allows efficient data transmission and reception. For more details onthe EMAC, see the TMS320C6000 DSP Ethernet Media Access Controller (EMAC) /Management Data Input/Output (MDIO) Module Reference Guide (literaturenumber SPRU628).

The management data input/output (MDIO) module continuously polls all 32 MDIOaddresses in order to enumerate all PHY devices in the system. Once a PHYcandidate has been selected by the DSP, the MDIO module transparently monitorsits link state by reading the PHY status register. Link change events are storedin the MDIO module and can optionally interrupt the DSP, allowing the DSP topoll the link status of the device without continuously performing costly MDIOaccesses. For more details on the MDIO, see the TMS320C6000 DSP EthernetMedia Access Controller (EMAC) / Management Data Input/Output (MDIO) ModuleReference Guide (literature number SPRU628).

The I2C0 port on the TMS320DM641/DM640 allows the DSP to easily controlperipheral devices and communicate with a host processor. In addition, thestandard multichannel buffered serial port (McBSP) may be used to communicatewith serial peripheral interface (SPI) mode peripheral devices.

The DM641/DM640 has a complete set of development tools which includes: a newC compiler, an assembly optimizer to simplify programming and scheduling, and aWindows debugger interface for visibility into source code

TMS320DM640AZDK4

Feature

  • High-Performance Digital Media Processor (TMS320DM641/TMS320DM640)
    • 2.5-, 2-, 1.67-ns Instruction Cycle Time
    • 400-, 500-, 600-MHz Clock Rate
    • Eight 32-Bit Instructions/Cycle
    • 3200, 4000, 4800 MIPS
    • Fully Software-Compatible With C64x
  • VelociTI.2 Extensions to VelociTI Advanced Very-Long-Instruction-Word VLIW) TMS320C64x DSP Core
    • Eight Highly Independent Functional Units With VelociTI.2 Extensions:
      • Six ALUs (32-/40-Bit), Each Supports Single 32-Bit, Dual 16-Bit, or Quad 8-Bit Arithmetic per Clock Cycle
      • Two Multipliers Support Four 16 x 16-Bit Multiplies (32-Bit Results) per Clock Cycle or Eight 8 x 8-Bit Multiplies (16-Bit Results) per Clock Cycle
    • Load-Store Architecture With Non-Aligned Support
    • 64 32-Bit General-Purpose Registers
    • Instruction Packing Reduces Code Size
    • All Instructions Conditional
  • Instruction Set Features
    • Byte-Addressable (8-/16-/32-/64-Bit Data)
    • 8-Bit Overflow Protection
    • Bit-Field Extract, Set, Clear
    • Normalization, Saturation, Bit-Counting
    • VelociTI.2 Increased Orthogonality
  • L1/L2 Memory Architecture
    • 128K-Bit (16K-Byte) L1P Program Cache (Direct Mapped)
    • 128K-Bit (16K-Byte) L1D Data Cache (2-Way Set-Associative)
    • 1M-Bit (128K-Byte) L2 Unified Mapped RAM/Cache (Flexible RAM/Cache Allocation)
  • Endianess: Little Endian, Big Endian
  • 32-Bit External Memory Interface (EMIF)
    • Glueless Interface to Asynchronous Memories (SRAM and EPROM) and Synchronous Memories (SDRAM, SBSRAM, ZBT SRAM, and FIFO)
    • 1024M-Byte Total Addressable External Memory Space
  • Enhanced Direct-Memory-Access (EDMA) Controller (64 Independent Channels)
  • 10/100 Mb/s Ethernet MAC (EMAC)
    • IEEE 802.3 Compliant
    • Media Independent Interface (MII)
    • 8 Independent Transmit (TX) and 1 Receive (RX) Channel
  • Management Data Input/Output (MDIO)
  • Two Configurable Video Ports (DM641)
  • One Configurable Video Port (DM640)
    • Providing a Glueless I/F to Common Video Decoder and Encoder Devices
    • Supports Multiple Resolutions and Video Standards
  • VCXO Interpolated Control Port (VIC)
    • Supports Audio/Video Synchronization
  • Host-Port Interface (HPI) [16-Bit] (DM641)
  • Multichannel Audio Serial Port (McASP)
    • Four Serial Data Pins
    • Wide Variety of I2S and Similar Bit Stream Format
    • Integrated Digital Audio I/F Transmitter Supports S/PDIF, IEC60958-1, AES-3, CP-430 Formats
  • Inter-Integrated Circuit (I2C) Bus
  • Two Multichannel Buffered Serial Ports
  • Three 32-Bit General-Purpose Timers
  • Eight General-Purpose I/O (GPIO) Pins
  • Flexible PLL Clock Generator
  • IEEE-1149.1 (JTAG) Boundary-Scan-Compatible
  • 548-Pin Ball Grid Array (BGA) Package (GDK and ZDK Suffixes), 0.8-mm Ball Pitch
  • 548-Pin Ball Grid Array (BGA) Package (GNZ and ZNZ Suffixes), 1.0-mm Ball Pitch
  • 0.13-μm/6-Level Cu Metal Process (CMOS)
  • 3.3-V I/Os, 1.2-V Internal (-400, -500)
  • 3.3-V I/Os, 1.4-V Internal (-600)

TMS320DM640AZDK4 Block Diagram
(Picture: Diagram)

Technical Parameters

  • Data Bus Width
  • 32 bit
  • Maximum Clock Frequency
  • 400 MHz
  • Device Million Instructions per Second
  • 3200 MIPs
  • Operating Supply Voltage
  • 1.2 V, 3.3 V
  • Maximum Operating Temperature
  • + 90 C
  • Package / Case
  • FCBGA
  • Mounting Style
  • SMD/SMT
  • Instruction Type
  • Fixed Point
  • Minimum Operating Temperature
  • 0 C
  • Packaging
  • Tube
  • Product
  • DSPs
  • Series
  • TMS320DM640
  • Factory Pack Quantity
  • 60
  • Tradename
  • DaVinci

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  • **泉賢***
    2020-01-24

    Arrived promptly, thanks

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