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TE28F640J3C-120

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Intel StrataFlash Memory (J3)

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TE28F640J3C-120 Product Details

Description

The Intel StrataFlash® memory family contains high-density memories organized as 32 Mbytes or 16Mwords (256-Mbit, available on the 0.18µm lithography process only), 16 Mbytes or 8 Mwords (128-Mbit), 8 Mbytes or 4 Mwords (64-Mbit), and 4 Mbytes or 2 Mwords (32-Mbit). These devices can be accessed as 8- or 16-bit words. The 128-Mbit device is organized as one-hundredtwenty-eight 128-Kbyte (131,072 bytes) erase blocks. The 64-Mbit device is organized as sixtyfour 128-Kbyte erase blocks while the 32-Mbit device contains thirty-two 128-Kbyte erase blocks. A 128-bit Protection Register has multiple uses, including unique flash device identification. The device’s optimized architecture and interface dramatically increases read performance by supporting page-mode reads. This read mode is ideal for non-clock memory systems. A Common Flash Interface (CFI) permits software algorithms to be used for entire families of devices. This allows device-independent, JEDEC ID-independent, and forward- and backwardcompatible software support for the specified flash device families. Flash vendors can standardize their existing interfaces for long-term compatibility. Scalable Command Set (SCS) allows a single, simple software driver in all host systems to work with all SCS-compliant flash memory devices, independent of system-level packaging (e.g., memory card, SIMM, or direct-to-board placement). Additionally, SCS provides the highest system/device data transfer rates and minimizes device and system-level implementation costs. A Command User Interface (CUI) serves as the interface between the system processor and internal operation of the device. A valid command sequence written to the CUI initiates device automation. An internal Write State Machine (WSM) automatically executes the algorithms and timings necessary for block erase, program, and lock-bit configuration operations. A block erase operation erases one of the device’s 128-Kbyte blocks typically within one second— independent of other blocks. Each block can be independently erased 100,000 times. Block erase suspend mode allows system software to suspend block erase to read or program data from any other block. Similarly, program suspend allows system software to suspend programming (byte/ word program and write-to-buffer operations) to read data or execute code from any other block that is not being suspended. Each device incorporates a Write Buffer of 32 bytes (16 words) to allow optimum programming performance. By using the Write Buffer, data is programmed in buffer increments. This feature can improve system program performance more than 20 times over non-Write Buffer writes. Blocks are selectively and individually lockable in-system.Individual block locking uses block lock-bits to lock and unlock blocks. Block lock-bits gate block erase and program operations. Lock-bit configuration operations set and clear lock-bits (Set Block Lock-Bit and Clear Block Lock-Bits commands). The Status Register indicates when the WSM’s block erase, program, or lock-bit configuration operation is finished. The STS (STATUS) output gives an additional indicator of WSM activity by providing both a hardware signal of status (versus software polling) and status masking (interrupt masking for background block erase, for example). Status indication using STS minimizes both CPU overhead and system power consumption. When configured in level mode (default mode), it acts as a RY/ BY# signal. When low, STS indicates that the WSM is performing a block erase, program, or lockbit configuration. STS-high indicates that the WSM is ready for a new command, block erase is 256-Mbit J3 (x8/x16) Datasheet 9 suspended (and programming is inactive), program is suspended, or the device is in reset/powerdown mode. Additionally, the configuration command allows the STS signal to be configured to pulse on completion of programming and/or block erases. Three CE signals are used to enable and disable the device. A unique CE logic design (see Table 13, “Chip Enable Truth Table” on page 33) reduces decoder logic typically required for multi-chip designs. External logic is not required when designing a single chip, a dual chip, or a 4- chip miniature card or SIMM module. The BYTE# signal allows either x8 or x16 read/writes to the device. BYTE#-low selects 8-bit mode; address A0 selects between the low byte and high byte. BYTE#-high enables 16-bit operation; address A1 becomes the lowest order address and address A0 is not used (don’t care). A device block diagram is shown in Figure 4 on page 14. When the device is disabled (see Table 13 on page 33), with CEx at VIH and RP# at VIH, the standby mode is enabled. When RP# is at VIL, a further power-down mode is enabled which minimizes power consumption and provides write protection during reset. A reset time (tPHQV) is required from RP# going high until data outputs are valid. Likewise, the device has a wake time (tPHWL) from RP#-high until writes to the CUI are recognized. With RP# at VIL, the WSM is reset and the Status Register is cleared.


TE28F640J3C-120

TE28F640J3C-120 Pinout
(Picture: Pinout)

TE28F640J3C-120 Block Diagram
(Picture: Diagram)

Technical Parameters

  • Manufacturer
  • INTEL
  • Packing
  • Tape & Reel (TR)/Cut Tape (CT)/Tray/Tube
  • RoHs Status
  • Lead free / RoHS Compliant
  • Package/Case
  • TSOP-56

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  • **osep***
    2020-03-28

    alles bestens; Danke

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1.We provide 90 days warranty.

2.If some of the items you received aren't of perfect quality, we would resiponsibly arrange your refund or replacement. But the items must remain their orginal condition.

FAQ:

Q: How does Jotrin guarantee that TE28F640J3C-120 is the original manufacturer or agent of INTEL?
We have a professional business development department to strictly test and verify the qualifications of INTEL original manufacturers and agents. All INTEL suppliers must pass the qualification review before they can publish their TE28F640J3C-120 devices; we pay more attention to the channels and quality of TE28F640J3C-120 products than any other customer. We strictly implement supplier audits, so you can purchase with confidence.
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You can use Jotrin's intelligent search engine, or filter by Memory category, or find it through Intel Corp Information page.
Q: Are the INTEL's TE28F640J3C-120 price and stock displayed on the platform accurate?
The INTEL's inventory fluctuates greatly and cannot be updated in time, it will be updated periodically within 24 hours. After submitting an order for TE28F640J3C-120, it is recommended to confirm the order with Jotrin salesperson or online customer service before payment.
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Note: It may take up to 24 hours before carriers will display tracking information. In normal conditions, Express delivery needs 3-5 days, Registered Mail needs 25-60 days.
Q: What is the process for returns or replacement of TE28F640J3C-120?
All goods will implement Pre-Shipment Inspection (PSI), selected at random from all batches of your order to do a systematic inspection before arranging the shipment. If there is something wrong with the TE28F640J3C120 we delivered, we will accept the replacement or return of the TE28F640J3C-120 only when all of the below conditions are fulfilled:
(1)Such as a deficiency in quantity, delivery of wrong items, and apparent external defects (breakage and rust, etc.), and we acknowledge such problems.
(2)We are informed of the defect described above within 90 days after the delivery of TE28F640J3C-120.
(3)The TE28F640J3C-120 is unused and only in the original unpacked packaging.
Two processes to return the products:
(1)Inform us within 90 days
(2)Obtain Requesting Return Authorizations
More details about return electronic components please see our Return & Change Policy.
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Intel
Intel Corporation is the world's largest semiconductor chip maker. Intel has been committed to the development of small, fast and energy-saving technologies to help mobile computing, desktop computin and data centers to achieve revolutionary advances in computing, and to promote fundamental changes...

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