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Qorivva 32-bit MCU, Power Arch core, 1.5MB Flash, 80MHz, -40/+125degC, Automotive Qualified, QFP 144
| Manufacturer : | NXP Semiconductor |
|---|---|
| Package/Case : | LQFP-144 |
| Product Categories : | Microprocessors and Microcontrollers , Microcontrollers (MCU) |
| Datasheet: | SPC5634MF2MLQ80 Datasheet (PDF) |
| RoHs Status: | Lead free/RoHS Compliant |
| In-stock: | 15000 |
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SPC5634MF2MLQ80 Product Details
Operating Parameters Fully static operation, 0 MHz � 80 MHz (plus 2% frequency modulation - 82 MHz) 150 C junction temperature operating range Low power design � Less than 400 mW power dissipation (nominal) � Designed for dynamic power management of core and peripherals � Software controlled clock gating of peripherals � Low power stop mode, with all clocks stopped Fabricated 90 nm process 1.2 V internal logic Single power supply with 5.25 V) with internal regulator to provide 3.3 V and 1.2 V for the core Input and output pins with 5.25 V) range � 35%/65% VDDE CMOS switch levels (with hysteresis) � Selectable hysteresis � Selectable slew rate control Nexus pins powered 3.3 V supply Designed with EMI reduction techniques � Phase-locked loop � Frequency modulation of system clock frequency � On-chip bypass capacitance � Selectable slew rate and drive strength
High performance e200z335 core processor 32-bit Power Architecture Book E programmer's model Variable Length Encoding Enhancements � Allows Power Architecture instruction set to be optionally encoded in a mixed 16 and 32-bit instructions � Results in smaller code size Single issue, 32-bit Power Architecture technology compliant CPU In-order execution and retirement Precise exception handling Branch processing unit � Dedicated branch address calculation adder � Branch acceleration using Branch Lookahead Instruction Buffer Load/store unit � One-cycle load latency � Fully pipelined � Big and Little Endian support � Misaligned access support � Zero load-to-use pipeline bubbles Thirty-two 64-bit general purpose registers (GPRs) Memory management unit (MMU) with 16-entry fully-associative translation look-aside buffer (TLB) Separate instruction bus and load/store bus Vectored interrupt support Interrupt latency @ 80 MHz (measured from interrupt request to execution of first instruction of interrupt exception handler)
This document contains information on a product under development. Freescale reserves the right to change or discontinue this product without notice. � Freescale Semiconductor, Inc., 2008-2012. All rights reserved.
Introduction.9 1.1 Document Overview.9 2.1 Device 2.2 MPC5634M feature core.9 2.2.2 Crossbar. 11 2.2.3 eDMA. 11 2.2.4 Interrupt FMPLL.12 2.2.6 Calibration FlexCAN.22 2.2.18 System timers.23 2.2.19 Software Watchdog Timer (SWT).24 2.2.20 Debug 2.3 MPC5634M series architecture.26 2.3.1 Block diagram.26 2.3.2 Block summary.27 Pinout and signal 3.1 144 LQFP 3.2 176 LQFP pinout 3.3 176 LQFP pinout 3.4 208 MAPBGA ballmap 3.5 208 MAPBGA ballmap only).34 3.6 Signal summary.35 3.7 Signal details.51 Electrical characteristics.56 4.1 Parameter classification.56 Maximum ratings. 56 Thermal characteristics. 58 4.3.1 General notes for specifications at maximum junction temperature. 60 4.4 Electromagnetic Interference (EMI) characteristics. 62 4.5 Electromagnetic static discharge (ESD) characteristics62 4.6 Power Management Control (PMC) and Power On Reset (POR) electrical specifications. 63 4.6.1 Regulator example. 67 4.6.2 Recommended power transistors. 69 4.7 Power up/down sequencing. 4.8 DC electrical specifications. 70 4.9 I/O Pad current specifications. 77 4.9.1 I/O pad VRC33 current specifications. 78 4.9.2 LVDS pad specifications. 79 4.10 Oscillator and PLLMRFM electrical characteristics. 80 4.11 Temperature sensor electrical characteristics. 82 4.12 eQADC electrical characteristics. 82 4.13 Platform flash controller electrical characteristics. 85 4.14 Flash memory electrical characteristics. 4.15 AC specifications. 87 4.15.1 Pad AC specifications. 4.16 AC timing. 90 4.16.1 IEEE 1149.1 interface timing. 90 4.16.2 Nexus timing. 93 4.16.3 Calibration bus interface timing. 96 4.16.4 eMIOS timing. 99 4.16.5 DSPI timing. 99 4.16.6 eQADC SSI timing. 105 Packages. 106 5.1 Package mechanical data. 5.1.1 144 LQFP. 5.1.2 176 LQFP. 5.1.3 208 MAPBGA. 113 Ordering information. 115 Document revision history. 4.2 4.3
MPC5634M Microcontroller Data Sheet, Rev. 9 2 Freescale SemiconductorNon-maskable interrupt (NMI) input for handling external events that must produce an immediate response, e.g., power down detection. On this device, the NMI input is connected to the Critical Interrupt Input. (May not be recoverable) Critical Interrupt input. For external interrupt sources that are higher priority than provided by the Interrupt Controller. (Always recoverable) New `Wait for Interrupt' instruction, to be used with new low power modes Reservation instructions for implementing read-modify-write accesses Signal processing extension (SPE) APU � Operating on all 32 GPRs that are all extended to 64 bits wide � Provides a full compliment of vector and scalar integer and floating point arithmetic operations (including integer vector MAC and MUL operations) (SIMD) � Provides rich array of extended 64-bit loads and stores to/from extended GPRs � Fully code compatible with e200z6 core Floating point (FPU) � IEEE 754 compatible with software wrapper � Scalar single precision in hardware, double precision with software library � Conversion instructions between single precision floating point and fixed point � Fully code compatible with e200z6 core Long cycle time instructions, except for guarded loads, do not increase interrupt latency Extensive system development support through Nexus debug port Advanced microcontroller bus architecture (AMBA) crossbar switch (XBAR) Three master ports, four slave ports � Masters: CPU Instruction bus; CPU Load/store bus (Nexus); eDMA � Slave: Flash; SRAM; Peripheral Bridge; calibration EBI 32-bit internal address bus, 64-bit internal data bus Enhanced direct memory access (eDMA) controller 32 channels support independent or 32-bit single value or block transfers Supports variable sized queues and circular queues Source and destination address registers are independently configured to post-increment or remain constant Each transfer is initiated by a peripheral, CPU, or eDMA channel request Each eDMA channel can optionally send an interrupt request to the CPU on completion of a single value or block transfer Interrupt controller (INTC) 191 peripheral interrupt request sources 8 software setable interrupt request sources 9-bit vector � Unique vector for each interrupt request source � Provided by hardware connection to processor or read from register Each interrupt source can be programmed to one of 16 priorities Preemption � Preemptive prioritized interrupt requests to processor � ISR at a higher priority preempts ISRs or tasks at lower priorities � Automatic pushing or popping of preempted priority to or from a LIFO � Ability to modify the ISR or task priority. Modifying the priority can be used to implement the Priority Ceiling Protocol for accessing shared resources. Low latency--three clocks from receipt of interrupt request from peripheral to interrupt request to processor
Technical Parameters
- Life Cycle Stage
- ACTIVE
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**rcom***2018-10-03
Great parts arrived in good shape. Thank you
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