Products > Integrated Circuits (ICs) > Counter ICs > SN74LV8154PWR
SN74LV8154PWR TSSOP-20
TI
  • SN74LV8154PWR
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SN74LV8154PWR

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Bipolar Power TO247 NPN 8A 150V; Package: TO-247; No of Pins: 3; Container: Rail; Qty per Container: 30,Counter Shift Registers Dual 16-Bit Binary w/3-State Output

Manufacturer :
Texas Instruments, Inc
Package/Case :
TSSOP-20
Product Categories :
Counter Shift Registers
Datasheet:
SN74LV8154PWR PDF
RoHs Status:
Rohs
Marking Code:
LV8154
In-stock:
1265

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SN74LV8154PWR Product Details

The SN74LV8154PWR device is a dual 16-bit binary counter with 3-state output registers, designed for 2-V to 5.5-V VCC operation.

The counters have dedicated clock inputs. The counters share a clocked storage register to sample and save the counter contents. Both counters share an asynchronous clear input. The 32-bit storage register can be mapped on the output bus 8-bits at a time. Four bus reads are needed to access the contents of both stored counts. The two counters can be chained by connecting RCOA. All clocks are positive edge triggered. All other inputs are active low.

This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.

For all available packages, see the orderable addendum at the end of the data sheet.

Feature

  • Can Be Used as Two 16-Bit Counters or a Single 32-Bit Counter
  • 8 bit counter read bus
  • 2-V to 5.5-V VCC Operation
  • Maximum tpd of 25 ns at 5 V (RCLK to Y)
  • Typical VOLP (Output Ground Bounce) < 0.7 V at VCC = 5 V, TA = 25°C
  • Typical VOHV (Output VOH Undershoot) > 4.4 V at VCC = 5 V, TA = 25°C
  • Ioff Supports Partial-Power-Down Mode Operation
  • Latch-Up Performance Exceeds 250 mAPer JESD 17
  • ESD Protection Exceeds JESD 22
    • 2000-V Human Body Model (A114-A)
    • 200-V Machine Model (A115-A)
    • 1000-V Charged-Device Model (C101)
Description

The SN74LV8154 device is a dual 16-bit binary counter with 3-state output registers, designed for 2-V to 5.5-V VCC operation.

The counters have dedicated clock inputs. The counters share a clocked storage register to sample and save the counter contents. Both counters share an asynchronous clear input. The 32-bit storage register can be mapped on the output bus 8-bits at a time. Four bus reads are needed to access the contents of both stored counts. The two counters can be chained by connecting RCOA. All clocks are positive edge triggered. All other inputs are active low.

This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.

For all available packages, see the orderable addendum at the end of the data sheet.

SN74LV8154PWR Block Diagram
(Picture: Diagram)

Technical Parameters

Logic Family 74LV Packaging Reel
Counting Sequence Up Mounting Style SMD/SMT
Operating Supply Voltage 2 V to 5.5 V Factory Pack Quantity 2000
Package / Case TSSOP-20

SN74LV8154PWR Documents

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