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  • SN74LS374N
TI/MOTOROLA

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SN74LS374N

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OCTAL D-TYPE TRANSPARENT LATCHES AND EDGE-TRIGGERED FLIP-FLOPS,Flip Flops Octal

  • Manufacturer :
  • TI/MOTOROLA
  • Package/Case :
  • DIP-20
  • Product Categories :
  • Flip Flops
  • RoHs Status:
  • Lead free / RoHS Compliant
  • Marking Code:
  • SN74LS374N
  • In-stock:
  • 30000

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SN74LS374N Product Details

These 8-bit registers feature 3-state outputs designed specifically for driving highly capacitive or relatively low-impedance loads. The high-impedance 3-state and increased high-logic-level drive provide these registers with the capability of being connected directly to and driving the bus lines in a bus-organized system without need for interface or pullup components. These devices are particularly attractive for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers.

The eight latches of the ’LS373 and ’S373 are transparent D-type latches, meaning that while the enable (C or CLK) input is high, the Q outputs follow the data (D) inputs. When C or CLK is taken low, the output is latched at the level of the data that was set up.

The eight flip-flops of the ’LS374 and ’S374 are edge-triggered D-type flip-flops. On the positive transition of the clock, the Q outputs are set to the logic states that were set up at the D inputs.

Schmitt-trigger buffered inputs at the enable/clock lines of the ’S373 and ’S374 devices simplify system design as ac and dc noise rejection is improved by typically 400 mV due to the input hysteresis. A buffered output-control (OC) input can be used to place the eight outputs in either a normal logic state (high or low logic levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly.

OC\ does not affect the internal operation of the latches or flip-flops. That is, the old data can be retained or new data can be entered, even while the outputs are off.

SN74LS374N

Feature

  • Choice of Eight Latches or Eight D-Type Flip-Flops in a Single Package
  • 3-State Bus-Driving Outputs
  • Full Parallel Access for Loading
  • Buffered Control Inputs
  • Clock-Enable Input Has Hysteresis to Improve Noise Rejection (’S373 and ’S374)
  • P-N-P Inputs Reduce DC Loading on Data Lines (’S373 and ’S374)
Description

These 8-bit registers feature 3-state outputs designed specifically for driving highly capacitive or relatively low-impedance loads. The high-impedance 3-state and increased high-logic-level drive provide these registers with the capability of being connected directly to and driving the bus lines in a bus-organized system without need for interface or pullup components. These devices are particularly attractive for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers.

The eight latches of the ’LS373 and ’S373 are transparent D-type latches, meaning that while the enable (C or CLK) input is high, the Q outputs follow the data (D) inputs. When C or CLK is taken low, the output is latched at the level of the data that was set up.

The eight flip-flops of the ’LS374 and ’S374 are edge-triggered D-type flip-flops. On the positive transition of the clock, the Q outputs are set to the logic states that were set up at the D inputs.

Schmitt-trigger buffered inputs at the enable/clock lines of the ’S373 and ’S374 devices simplify system design as ac and dc noise rejection is improved by typically 400 mV due to the input hysteresis. A buffered output-control (OC) input can be used to place the eight outputs in either a normal logic state (high or low logic levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly.

OC\ does not affect the internal operation of the latches or flip-flops. That is, the old data can be retained or new data can be entered, even while the outputs are off.

Technical Parameters

  • Number of Circuits
  • 8
  • Logic Family
  • 74LS
  • Logic Type
  • Transparent D-Type Latch
  • Polarity
  • Non-Inverting
  • Input Type
  • Parallel / Parallel
  • Output Type
  • Single-Ended
  • Propagation Delay Time
  • 28 ns
  • High Level Output Current
  • - 2.6 mA
  • Low Level Output Current
  • 24 mA
  • Supply Voltage Max
  • 5.25 V
  • Maximum Operating Temperature
  • + 70 C
  • Mounting Style
  • Through Hole
  • Package / Case
  • PDIP-20
  • Packaging
  • Tube
  • Minimum Operating Temperature
  • 0 C
  • Number of Input Lines
  • 4
  • Number of Output Lines
  • 2
  • Factory Pack Quantity
  • 20
  • Supply Voltage Min
  • 4.75 V

SN74LS374N Documents

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  • **ob S***
    2020-03-28

    quickly received

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We have a professional business development department to strictly test and verify the qualifications of TI/MOTOROLA original manufacturers and agents. All TI/MOTOROLA suppliers must pass the qualification review before they can publish their SN74LS374N devices; we pay more attention to the channels and quality of SN74LS374N products than any other customer. We strictly implement supplier audits, so you can purchase with confidence.
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You can use Jotrin's intelligent search engine, or filter by Semiconductors ; Logic ; Flip-flop/latch/register category, or find it through TI/MOTOROLA brand manufacturer page.
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