MCU 16Bit/32Bit Hercules RM ARM Cortex R4F RISC 2048KB Flash 1.2V/3.3V 337Pin NFBGA
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RM48L540DZWTT Product Details
TheRM48Lx40 device is ahigh-performance microcontroller family forsafety systems. The safety architecture includesdual CPUs in lockstep, CPUand memory BIST logic, ECC on both the flash and the data SRAM, parityonperipheral memories, and loopback capability on peripheral I/Os.
The RM48Lx40deviceintegrates the ARM Cortex-R4FFloating-PointCPU. The CPU offers an efficient 1.66 DMIPS/MHz, and hasconfigurations thatcan run up to 200MHz, providing up to 332 DMIPS.The device supports thelittle-endian [LE]format.
The RM48L940 device has 3MB of integrated flash and 256KB of data RAM. TheRM48L740 device has 2MB of integrated flash and 256KB of data RAM. The RM48L540device has 2MB ofintegrated flash and 192KB of data RAM.Both the flash and RAM have single-bit error correction and double-bit error detection. Theflash memory on thisdevice is a nonvolatile, electrically erasable, andprogrammable memory implemented with a64-bit-wide data bus interface. Theflash operates on a 3.3-V supply input (same level as I/Osupply) for allread, program, and erase operations. When in pipeline mode, the flash operateswitha system clock frequency of up to 200 MHz.The SRAM supportssingle-cycle read and write accesses in byte, halfword, word, and double-wordmodes.
The RM48Lx40devicefeatures peripherals for real-time control-basedapplications, including twoNext Generation High-End Timer (N2HET) timingcoprocessors and two 12-bit Analog-to-DigitalConverters (ADCs) supporting upto 24 inputs.
The N2HET is an advanced intelligent timer that provides sophisticated timingfunctionsfor real-time applications. The timer is software-controlled, usinga reduced instruction set, witha specialized timer micromachine and anattached I/O port. The N2HET can be used forpulse-width-modulated outputs,capture or compare inputs, or GPIO. The N2HET is especially wellsuited forapplications requiring multiple sensor information and drive actuators withcomplex andaccurate time pulses. A High-End Timer Transfer Unit (HTU) canperform DMA-type transactions totransfer N2HET data to or from main memory.A Memory Protection Unit (MPU) is built into theHTU.
Thedevice has two 12-bit-resolution MibADCs with 24 channels and 64 wordsof parity-protected bufferRAM each. The MibADC channels can be convertedindividually or can be grouped by software forsequential conversionsequences. Sixteen channels are shared between the two MibADCs. There arethree separate groupings. Each sequence can be converted once when triggered orconfigured forcontinuous conversion mode. The MibADC has a 10-bit mode foruse when compatibility with olderdevices or faster conversion time isdesired.
Thedevice has multiple communication interfaces: three MibSPIs,twoSPIs, one LIN, one SCI, three DCANs,one I2C module, and oneEthernet. TheSPIsprovide a convenient method of serial high-speed communication betweensimilar shift-register typedevices. The LIN supports the Local Interconnectstandard 2.0 and can be used as a UART infull-duplex mode using the standardNon-Return-to-Zero (NRZ) format.
TheDCAN supports the CAN 2.0 (A and B) protocol standard and uses aserial, multimaster communicationprotocol that efficiently supportsdistributed real-time control with robust communication rates ofup to 1Mbps. The DCAN is ideal for systems operating in noisy and harsh environments(for example,automotive vehicle networking and industrial fieldbus) thatrequire reliable serial communicationor multiplexed wiring.
The Ethernet module supports MII, RMII, and MDIO interfaces.
TheI2C module is a multimaster communication module providing aninterface between the microcontrollerand an I2C-compatible devicethrough the I2Cserial bus. The I2C supports speeds of100 and 400 Kbps.
The Frequency-Modulated Phase-Locked Loop (FMPLL) clock module is used tomultiply theexternal frequency reference to a higher frequency for internaluse. There are two FMPLL modules onthis device. These modules, when enabled,provide two of the seven possible clock source inputs tothe Global ClockModule (GCM). The GCM manages the mapping between the available clock sourcesandthe device clock domains.
The device also has an External Clock Prescaler (ECP) module that whenenabled, outputsa continuous external clock on the ECLK pin (or ball). TheECLK frequency is a user-programmableratio of the peripheral interface clock(VCLK) frequency. This low-frequency output can bemonitored externally as anindicator of the device operating frequency.
The DMA controller has 16 channels, 32 peripheral requests, and parityprotection on its memory. An MPU is built into the DMA to limit the DMA toprescribed areas ofmemory and to protect the rest of the memory system fromany malfunction of the DMA.
The Error Signaling Module (ESM) monitors all device errors and determineswhether aninterrupt is generated or the external ERRORpin is toggled when a fault isdetected. The ERRORpin can be monitored externally as an indicator of afault condition in themicrocontroller.
TheExternal Memory Interface (EMIF) provides off-chip expansioncapability with the ability tointerface to synchronous DRAM (SDRAM) devices,asynchronous memories, peripherals, or FPGAdevices.
Severalinterfaces are implemented to enhance the debugging capabilitiesof application code. In additionto the built-in ARM Cortex-R4F CoreSightdebug features, an External Trace Macrocell (ETM) providesinstruction anddata trace of program execution. For instrumentation purposes, a RAM Trace Port (RTP) module is implemented to support high-speed tracing of RAM andperipheral accesses by the CPUor any other master. A Data ModificationModule (DMM) gives the ability to write external data intothe device memory.Both the RTP and DMM have no or only minimum impact on the program executiontime of the application code. A Parameter Overlay Module (POM) can reroute flashaccesses tointernal memory or to the EMIF. This rerouting allows the dynamiccalibration against productioncode of parameters and tables withoutrebuilding the code to explicitly access RAM or halting theprocessor toreprogram the data flash.
With integrated safety features and a wide choice of communication andcontrolperipherals, the RM48Lx40 device is anideal solution forhigh-performance real-time control applications with safety-critical
- High-Performance Microcontroller for Safety-Critical Applications
- Dual CPUs Running in Lockstep
- ECC on Flash and RAM Interfaces
- Built-In Self-Test (BIST) for CPU and On-chip RAMs
- Error Signaling Module With Error Pin
- Voltage and Clock Monitoring
- ARM Cortex-R4F 32-Bit RISC CPU
- Efficient 1.66 DMIPS/MHz With 8-Stage Pipeline
- FPU With Single- and Double-Precision
- 12-Region Memory Protection Unit (MPU)
- Open Architecture With Third-Party Support
- Operating Conditions
- System Clock up to 200 MHz
- Core Supply Voltage (VCC): 1.2 V Nominal
- I/O Supply Voltage (VCCIO): 3.3 V Nominal
- ADC Supply Voltage (VCCAD): 3.0 to 5.25 V
- Integrated Memory
- 3MB of Program Flash With ECC (RM48L940)
- 2MB of Program Flash With ECC (RM48L740/540)
- 256KB of RAM With ECC (RM48L940/740)
- 192KB of RAM With ECC (RM48L540)
- 64KB of Flash With ECC for Emulated EEPROM
- 16-Bit External Memory Interface
- Common Platform Architecture
- Consistent Memory Map Across Family
- Real-Time Interrupt (RTI) Timer OS Timer
- 96-Channel Vectored Interrupt Module (VIM)
- 2-Channel Cyclic Redundancy Checker (CRC)
- Direct Memory Access (DMA) Controller
- 16 Channels and 32 Peripheral Requests
- Parity Protection for Control Packet RAM
- DMA Accesses Protected by Dedicated MPU
- Frequency-Modulated Phase-Locked Loop (FMPLL) With Built-In SlipDetector
- Separate Nonmodulating PLL
- Trace and Calibration Capabilities
- Embedded Trace Macrocell (ETM-R4)
- Data Modification Module (DMM)
- RAM Trace Port (RTP)
- Parameter Overlay Module (POM)
- Multiple Communication Interfaces
- 10/100 Mbps Ethernet MAC (EMAC)
- IEEE 802.3 Compliant (3.3-V I/O Only)
- Supports MII, RMII, and MDIO
- Three CAN Controllers (DCANs)
- 64 Mailboxes, Each With Parity Protection
- Compliant to CAN Protocol Version 2.0B
- Standard Serial Communication Interface (SCI)
- Local Interconnect Network (LIN) Interface Controller
- Compliant to LIN Protocol Version 2.1
- Can be Configured as a Second SCI
- Inter-Integrated Circuit (I2C)
- Three Multibuffered Serial Peripheral Interfaces (MibSPIs)
- 128 Words With Parity Protection Each
- Two Standard Serial Peripheral Interfaces (SPIs)
- 10/100 Mbps Ethernet MAC (EMAC)
- Two Next Generation High-End Timer (N2HET) Modules
- N2HET1: 32 Programmable Channels
- N2HET2: 18 Programmable Channels
- 160-Word Instruction RAM Each With Parity Protection
- Each N2HET Includes Hardware Angle Generator
- Dedicated High-End Transfer Unit (HTU) With MPU for Each N2HET
- Two 12-Bit Multibuffered ADC Modules
- ADC1: 24 Channels
- ADC2: 16 Channels Shared With ADC1
- 64 Result Buffers With Parity Protection Each
- General-Purpose Input/Output (GPIO) Pins Capable of GeneratingInterrupts
- 16 Pins on the ZWT Package
- 10 Pins on the PGE Package
- IEEE 1149.1 JTAG, Boundary Scan and ARM CoreSight Components
- JTAG Security Module
- 144-Pin Quad Flatpack (PGE) [Green]
- 337-Ball Grid Array (ZWT) [Green]
|Frequency||200 MHz||Product Lifecycle Status||Active|
|Clock Speed||200 MHz||Packaging||Tray|
|RAM Memory Size||196608 B||Case/Package||LFBGA|
|FLASH Memory Size||2097152 B||RoHS||Compliant|
|Number of UARTs||2||Lead Free Status||Lead Free|
RM48L540 Family Datasheet
RM48L540DZWTT Related Products
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Estimated Delivery Time: Dec 11 - Dec 16 days (choose Expedited at checkout).
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