Products > Integrated Circuits (ICs) > Embedded Processors & Controllers > RM46L450ZWTT
RM46L450ZWTT 337-LFBGA
TI
  • RM46L450ZWTT
  • RM46L450ZWTT 1
Images are for reference only.

RM46L450ZWTT

MCU 16Bit/32Bit Hercules RM ARM Cortex R4F RISC 1024KB Flash 1.2V 337Pin NFBGA

Manufacturer :
Texas Instruments, Inc
Package/Case :
337-LFBGA
Product Categories :
Microcontrollers
Datasheet:
RM46L450ZWTT PDF
RoHs Status:
Green
In-stock:
291

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RM46L450ZWTT Product Details

The RM46Lx50 deviceis a high-performance microcontroller family forsafety systems. The safety architecture includesdual CPUs in lockstep, CPUand memory BIST logic, ECC on both the flash and the data SRAM, parityonperipheral memories, and loopback capability on peripheral I/Os.

The RM46Lx50 deviceintegrates the ARM Cortex-R4Ffloating-pointCPU which offers an efficient 1.66 DMIPS/MHz, andcan run up to 200 MHzprovidingup to 332 DMIPS.The device supports the little-endian [LE]format.

The RM46L850 devicehas 1.25MB of integratedflash and 192KB ofdata RAM with single-bit error correction and double-bit error detection. TheRM46L450device has 1MBof integrated flash and 128KB of data RAM withsingle-bit error correction and double-bit errordetection. The flash memoryon this device is a nonvolatile, electrically erasable andprogrammablememory, implemented with a 64-bit-wide data bus interface. The flash operates ona3.3-V supply input (same level as I/O supply) for all read, program, anderase operations. When inpipeline mode, the flash operates with a systemclock frequency of up to 200 MHz. The SRAMsupports single-cycle read andwrite accesses in byte, halfword, word, and double-word modesthroughout thesupported frequency range.

The RM46Lx50 devicefeatures peripherals for real-time control-basedapplications, includingtwo Next Generation High-End Timer (N2HET) timingcoprocessorswith up to 44 I/O terminals, seven Enhanced Pulse WidthModulator (ePWM) modules with up to 14outputs, six Enhanced Capture (eCAP)modules, two Enhanced Quadrature Encoder Pulse (eQEP) modules,and two 12-bitAnalog-to-Digital Converters (ADCs) supporting up to 24 inputs.

The N2HET is an advanced intelligent timer that provides sophisticated timingfunctionsfor real-time applications. The timer is software-controlled, usinga reduced instruction set, witha specialized timer micromachine and anattached I/O port. The N2HET can be used forpulse-width-modulated outputs,capture or compare inputs, or general-purpose I/O (GIO). The N2HETisespecially well suited for applications requiring multiple sensor informationand driveactuators with complex and accurate time pulses. A High-End TimerTransfer Unit (HTU) can performDMA-type transactions to transfer N2HET datato or from main memory. A Memory Protection Unit (MPU)is built into theHTU.

TheePWM module can generate complex pulse width waveforms with minimalCPU overhead or intervention.The ePWM is easy to use and it supports bothhigh-side and low-side PWM and deadband generation.With integrated trip zoneprotection and synchronization with the on-chip MibADC, the ePWM moduleisideal for digital motor control applications.

TheeCAP module is essential in systems where the accurately timed captureof external events isimportant. The eCAP can also be used to monitor theePWM outputs or for simple PWM generation whenthe eCAP is not needed forcapture applications.

TheeQEP module is used for direct interface with a linear or rotaryincremental encoder to getposition, direction, and speed information from arotating machine as used in high-performancemotion and position-controlsystems.

The device hastwo12-bit-resolutionMibADCs with24 total inputsand 64 wordsof parity-protected buffer RAM each. The MibADC channels can beconverted individually or can begrouped by software for sequentialconversion sequences.Sixteeninputs are shared between the two MibADCs.Each MibADC supports three separate groupings ofchannels. Each group can beconverted once when triggered or configured for continuous conversionmode.The MibADC has a 10-bit mode for use when compatibility with older devices orfaster conversiontime is desired.MibADC1 also supports the use ofexternal analog multiplexers.

The device has multiple communication interfaces:three MibSPIs,twoSPIs, one LIN,oneSCI, three DCANs,one I2C,oneEthernet, and one USB module. The SPIprovides a convenient method of serialhigh-speed communications between similar shift-registertype devices. TheLIN supports the Local Interconnect standard 2.0 and can be used as a UART infull-duplex mode using the standard Non-Return-to-Zero (NRZ) format. The DCANsupports the CAN 2.0(A and B) protocol standard and uses a serial,multimaster communication protocol that efficientlysupports distributedreal-time control with robust communication rates of up to 1 Mbps. The DCAN isideal for systems operating in noisy and harsh environments (for example,automotive and industrialfields) that require reliable serial communicationor multiplexed wiring. The Ethernet module supports MII, RMII, andMDIOinterfaces.

The USB module includes a 2-port USB hostcontroller that is revision2.0-compatible, based on the OHCI specification for USB, release 1.0.The USBmodule also includes a USB device controller compatible with the USBspecification revision2.0 and USB specification revision 1.1.

TheI2C module is a multimaster communication module providing aninterface between the microcontrollerand an I2C-compatible devicethrough the I2Cserial bus. The I2C supports speeds of100 and 400 Kbps.

A Frequency-Modulated Phase-Locked Loop (FMPLL) clock module is used tomultiply theexternal frequency reference to a higher frequency for internaluse.The Global Clock Module (GCM) manages the mapping between the availableclock sources and thedevice clock domains.

The device also has an External Clock Prescaler (ECP) module that whenenabled, outputsa continuous external clock on the ECLK terminal. The ECLKfrequency is a user-programmable ratioof the peripheral interface clock(VCLK) frequency. This low-frequency output can be monitoredexternally as anindicator of the device operating frequency.

The Direct Memory Access (DMA) controller has 16 channels, 32 peripheralrequests,and parity protection on its memory. An MPU is built into the DMAto protect memory againsterroneous transfers.

The Error Signaling Module (ESM) monitors all device errors and determineswhether aninterrupt or external error pin (ball) is triggered when a faultis detected. The nERROR terminalcan be monitored externally as an indicatorof a fault condition in the microcontroller.

TheExternal Memory Interface (EMIF) provides a memory extension toasynchronous and synchronousmemories or other slave devices.

AParameter Overlay Module (POM) enhances the calibration capabilities ofapplication code. The POMcan reroute flash accesses to internal memory or tothe EMIF, thus avoiding the reprogramming stepsnecessary for parameterupdates in flash.

With integrated safety features and a wide choice of communication andcontrolperipherals, the RM46Lx50deviceis an ideal solution forhigh-performance real-time control applications with safety-critical

Feature

  • High-Performance Microcontroller for Safety-Critical Applications
    • Dual CPUs Running in Lockstep
    • ECC on Flash and RAM Interfaces
    • Built-In Self-Test (BIST) for CPU and On-chip RAMs
    • Error Signaling Module With Error Pin
    • Voltage and Clock Monitoring
  • ARM Cortex-R4F 32-Bit RISC CPU
    • 1.66 DMIPS/MHz With 8-Stage Pipeline
    • FPU With Single- and Double-Precision
    • 12-Region Memory Protection Unit (MPU)
    • Open Architecture With Third-Party Support
  • Operating Conditions
    • Up to 200-MHz System Clock
    • Core Supply Voltage (VCC): 1.14 to 1.32 V
    • I/O Supply Voltage (VCCIO): 3.0 to 3.6 V
  • Integrated Memory
    • 1.25MB of Program Flash With ECC (RM46L850)
    • 1MB of Program Flash With ECC (RM46L450)
    • 192KB of RAM With ECC (RM46L850)
    • 128KB of RAM With ECC (RM46L450)
    • 64KB of Flash for Emulated EEPROM With ECC
  • 16-Bit External Memory Interface (EMIF)
  • Common Platform Architecture
    • Consistent Memory Map Across Family
    • Real-Time Interrupt (RTI) Timer (OS Timer)
    • 128-Channel Vectored Interrupt Module (VIM)
    • 2-Channel Cyclic Redundancy Checker (CRC)
  • Direct Memory Access (DMA) Controller
    • 16 Channels and 32 Peripheral Requests
    • Parity Protection for Control Packet RAM
    • DMA Accesses Protected by Dedicated MPU
  • Frequency-Modulated Phase-Locked Loop (FMPLL) With Built-In SlipDetector
  • Separate Nonmodulating PLL
  • IEEE 1149.1 JTAG, Boundary Scan and ARM CoreSight Components
  • Advanced JTAG Security Module (AJSM)
  • Calibration Capabilities
    • Parameter Overlay Module (POM)
  • 16 General-Purpose Input/Output (GPIO) Pins Capable of GeneratingInterrupts
  • Enhanced Timing Peripherals for Motor Control
    • 7 Enhanced Pulse Width Modulator (ePWM) Modules
    • 6 Enhanced Capture (eCAP) Modules
    • 2 Enhanced Quadrature Encoder Pulse (eQEP) Modules
  • Two Next Generation High-End Timer (N2HET) Modules
    • N2HET1: 32 Programmable Channels
    • N2HET2: 18 Programmable Channels
    • 160-Word Instruction RAM Each With Parity Protection
    • Each N2HET Includes Hardware Angle Generator
    • Dedicated High-End Timer Transfer Unit (HTU) for Each N2HET
  • Two 12-Bit Multibuffered Analog-to-Digital Converter (MibADC)Modules
    • ADC1: 24 Channels
    • ADC2: 16 Channels Shared With ADC1
    • 64 Result Buffers Each With Parity Protection
  • Multiple Communication Interfaces
    • 10/100 Mbps Ethernet MAC (EMAC)
      • IEEE 802.3 Compliant (3.3-V I/O Only)
      • Supports MII, RMII, and MDIO
    • USB
      • 2-Port USB Host Controller
      • One Full-Speed USB Device Port
    • Three CAN Controllers (DCANs)
      • 64 Mailboxes Each With Parity Protection
      • Compliant to CAN Protocol Version 2.0A and 2.0B
    • Inter-Integrated Circuit (I2C)
    • Three Multibuffered Serial Peripheral Interface (MibSPI) Modules
      • 128 Words Each With Parity Protection
      • 8 Transfer Groups
    • Up to Two Standard Serial Peripheral Interface (SPI) Modules
    • Two UART (SCI) Interfaces, One With Local Interconnect Network (LIN2.1) Interface Support
  • Packages
    • 144-Pin Quad Flatpack (PGE) [Green]
    • 337-Ball Grid Array (ZWT) [Green]

RM46L450ZWTT Block Diagram
(Picture: Diagram)

Technical Parameters

Frequency 200 MHz Product Lifecycle Status Active
Clock Speed 200 MHz Packaging Tray
RAM Memory Size 131072 B Case/Package FBGA
FLASH Memory Size 1048576 B RoHS Compliant
Number of UARTs 2 Lead Free Status Lead Free

RM46L450ZWTT Documents

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(1)Such as a deficiency in quantity, delivery of wrong items, and apparent external defects (breakage and rust, etc.), and we acknowledge such problems.
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