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  • PM8611-PI
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PM8611-PI

Telecom Interface ICs SBI Bus Serializer for One 77MHz SBI336 Bus

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  • BGA-160
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  • Communication & Networking ICs
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PM8611-PI Product Details

The PM8611-PI SBI336 Bus Serializer, SBSLITE, is a monolithic integrated circuit that implements conversion between a byte-serial 77.76MHz SBI336 bus and redundant 777.6Mbps bit-serial 8B/10B-base SBI336S bus. In TelecomBus mode the SBSLITE implements conversion between a 77.76MHz TelecomBus format and redundant 777.6Mbps bit-serial 8B/10B-base serial TelecomBus format. In line with the bus conversion is a DS0 granular switch allowing any input DS0 to be output on any output DS0. 

The SBSLITE can be used to connect and switch high-density T1/E1 framer devices supporting an SBI bus with link layer devices supporting an SBI bus over a serial backplane. Putting the Narrowband Switch Element, NSE, between the framer and link layer devices allows construction of up to 20Gb/s NxDS0 switches. 

In the ingress direction, the SBSLITE connects an incoming 77.76MHz SBI336 stream to a pair of redundant serial SBI336S LVDS links through a DS0 memory switch. In TelecomBus mode an incoming 77.76MHz TelecomBus that has the J1 path fixed and all high order pointer justifications converted to tributary pointer justifications can be switched through a VT/TU granular switch to a pair of redundant serial LVDS TelecomBus format links. The incoming data is encoded into an extended set of 8B/10B characters and transferred onto two redundant 777.6 Mbps serial LVDS links. SBI or TelecomBus frame boundaries, pointer justification events and master timing controls are marked by 8B/10B control characters. Incoming SPEs may be optionally overwritten with the locally generated X23 + X18 + 1 PRBS pattern for diagnosis of downstream equipment. The PRBS processor is configurable to handle any combination of SPEs and can be inserted independently into either of the redundant LVDS links. A DS0 memory switch provides arbitrary mapping of streams on the incoming SBI336 bus stream to the working and protect LVDS links at DS0 granularity. In TelecomBus mode a VT/TU memory switch provides arbitrary mapping of tributaries on the incoming TelecomBus stream to the working and protect LVDS links. Multi-cast is supported. 

In the egress direction, the SBSLITE connects two independent 777.6 Mbps serial LVDS links to an outgoing SBI336 Bus. Each link contains a constituent SBI336S stream. Bytes on the links are carried as 8B/10B characters. The SBSLITE decodes the characters into data and control signals for a single 77.76MHz SBI336 bus. Alternatively the SBSLITE decodes two independent 777.6 Mbps TelecomBus formatted serial LVDS links characters into a single 77.76MHz TelecomBus. A pseudo-random bit sequence (PRBS) processor is provided to monitor the decoded payload for the X23 + X18 + 1 pattern in each SPE. The PRBS processor is configurable to handle any combination of SPEs in the serial LVDS link. Data on the outgoing SBI336 bus stream may be sourced from either of the LVDS links. 

An In-band signaling link over the serial LVDS links allows this device to be controlled by a companion-switching device, the Narrowband Switching Element, NSE20G. This link can be used as communication link between a central processor and the local microprocessor. 

Two loop backs are provided on the SBSLITE. The transmit 8b/10b to receive 8b/10b loop back allows data entering on the incoming bus to be looped back from the output of the TW8E and TP8E to the input of the RW8D and RP8D, respectively. Only the data looped back on the active link (working or protection) will make it back to the outgoing bus. The transmit to receive loop back allows data entering on the incoming bus to be looped back from the output of the ICASM to the input of the OCASE and then returned to the outgoing bus.

Feature

• SBI converter and TDM SBI switch 

• Byte wide 77.76MHz SBI336 bus to 777.6MHz serial SBI336S converter. 

• DS0, NxDS0, T1, E1, TVT1.5, TVT2, DS3 and E3 granular SBI336 to serial SBI336S switch. Supports sub-rate link switching with the restriction that sub-rate links must be symmetric in both the transmit and receive directions. 

• VT/TU channelized TelecomBus to TelecomBus converter and TDM switch. 

• Byte wide 77.76MHz TelecomBus to serial 777.6MHz TelecomBus converter. 

• VT/TU, STS/AU 77.76MHz TelecomBus to serial TelecomBus switch. 

• With the Narrowband Switch Element, NSE, the SBSLITE can be used to implement a DS0 granularity SBI Memory:Space:Memory switch scaleable to 20Gb/s. In TelecomBus mode a 20Gb/s VT/TU granularity Memory:Space:Memory switch can be implemented. 

• Integrates two independent DS0 granularity Memory Switches. One switch is placed between the incoming 77.76MHz byte wide SBI336 bus and the transmit working and protect Serial SBI336S link. The transmit working and protect links transmit the same data. The other switch is placed between the receive working or protect Serial SBI336S link and the outgoing 77.76MHz byte wide SBI336 bus. 

• Nominal latency through the SBSLITE in DS0 mode is 125uS. Channel Associated Signaling (CAS) latency through the SBSLITE in DS0 mode is two T1 multi-frame (6mS) or two E1 multi-frame (4mS). 

• In TelecomBus mode or SBI mode without DS0 level switching nominal latency through the SBSLITE is <15uS. 

• The Memory Switch permits any receive or incoming byte from an input port to be mapped to any outgoing or transmit byte, respectively, on the associated output port 

• Supports redundant working and protect serial SBI336S links in support of a redundant Memory:Space:Memory switch with the NSE. 

• Encodes and decodes byte wide SBI336 bus control signals for all SBI supported link types and clock modes for transport over the serial SBI336S interface. 

• Encodes data from the Incoming SBI336 bus or TelecomBus stream to a working and protect 777.6Mbps LVDS serial links with 8B/10B-based encoding. 

• Decodes data from a working and protect 777.6MHz LVDS serial links with 8B/10B-based encoding to the Outgoing SBI336 bus or TelecomBus stream. 

• In SBI mode switches Channel Associated Signaling bits, CAS, with all DS0 data. 

• Uses 8B/10B-based line coding protocol on the serial links to provide transition density guarantee and DC balance and to offer a greater control character vocabulary than the standard 8B/10B protocol. 

• Provides optional PRBS generation for each outgoing LVDS serial data link for off-line link verification. PRBS can be inserted with STS/AU granularity. 

• Provides PRBS detection for each incoming LVDS serial link for off-line link verification. PRBS is verified with STS/AU granularity. 

• Provides pins to coordinate updating of the connection map of the memory switch blocks in the local device, peer SBSLITE devices and companion NSE switch device. 

• Can communicate with the NSE switch device over an in-band communications channel in the LVDS links. This channel includes mechanisms for central control and configuration. 

• Derives all internal timing from a single 77.76MHz system clock. 

• Implemented in 1.8V/3.3V 0.18μm CMOS and packaged in a 160 ball 15mmx15mm PBGA. 

• Low power consumption of 0.95W (typical). 

Applications

• T1/E1 SONET/SDH Cross-connects 

• T1/E1 SONET/SDH Add-Drop Multiplexers 

• Multi-service Access Multiplexers 

• Multi-Service Switches (MSS) 

• Multi-service Provisioning Platforms (MSPP) 

• Serial Backplane Board Interconnect 

• Shelf to Shelf Cabled Serial Interconnect 

• Voice/Media Gateways 

PM8611-PI Pinout
(Picture: Pinout)

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  • BGA-160

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  • **김상구***
    2020-01-30

    Thank you very much!, 1A-supplier!

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