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Level Translating Fm+ I2C-Bus Repeater, 2 Input, 2.2 V to 5.5 V, HWSON-8
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PCA9617ATPZ Product Details
The is a CMOS integrated circuit that provides level shifting between low voltage 5.5 V) and higher voltage 5.5 V) Fast-mode Plus (Fm+) I2C-bus or SMBus applications. While retaining all the operating modes and features of the I2C-bus system during the level shifts, it also permits extension of the I2C-bus by providing bidirectional buffering for both the data (SDA) and the clock (SCL) lines, thus enabling two buses at 1 MHz pF at lower speeds. Using the PCA9617ATPZ enables the system designer to isolate two halves of a bus for both voltage and capacitance. The SDA and SCL pins are overvoltage tolerant and are high-impedance when the PCA9617ATPZ is unpowered. The 5.5 V bus port B drivers have the static level offset, while the adjustable voltage bus port A drivers eliminate the static offset voltage. This results in a LOW on the port B translating into a nearly 0 V LOW on the port A which accommodates the smaller voltage swings of lower voltage logic. The static offset design of the port B PCA9617ATPZ I/O drivers prevents them from being connected to the static or incremented offset of other bus buffers. Port A of two or more PCA9617As can be connected together, however, to allow a star topography with port A on the common bus, and port A can be connected directly to any other buffer with static or incremented offset outputs. Multiple PCA9617As can be connected in series, port A to port B, with no build-up in offset voltage with only time of flight delays to consider. The PCA9617ATPZ drivers are not enabled unless VCC(A) is above 0.8 V and VCC(B) is above 2.2 V. The EN pin is referenced to VCC(B) and can also be used to turn the drivers on and off under system control. Caution should be observed to only change the state of the enable pin when the bus is idle. The output pull-down on the port B internal buffer LOW is set for approximately 0.55 V, while the input threshold of the internal buffer is set about 90 mV lower (0.45 V). When the port B I/O is driven LOW internally, the LOW is not recognized as a LOW by the input. This prevents a latching condition from occurring. The output pull-down on port A drives a hard LOW and the input level is set 0.35VCC(A) to accommodate the need for a lower LOW level in systems where the low voltage side supply voltage is as low 0.8 V.
2 channel, bidirectional buffer isolates capacitance and allows pF on either side of the device at 1 MHz and pF at lower speeds Voltage level translation from 5.5 V and from 5.5 V Footprint and functional replacement for PCA9517A at Fast-mode speeds Port A operating supply voltage range 5.5 V with normal levels
Port B operating supply voltage range 5.5 V with static offset level 5 V tolerant I2C-bus and enable pins to 1000 kHz clock frequency (the maximum system operating frequency may be less than 1000 kHz because of the delays added by the repeater) Active HIGH repeater enable input referenced to VCC(B) Open-drain input/outputs Latching free operation Supports arbitration and clock stretching across the repeater Accommodates Standard-mode, Fast-mode and Fast-mode Plus I2C-bus devices, SMBus (standard and high power mode), PMBus and multiple masters Powered-off high-impedance I2C-bus pins ESD protection exceeds 5500 V HBM per JESD22-A114 and 1000 V CDM per JESD22-C101 Latch-up testing is done to JEDEC Standard JESD78 which exceeds 100 mA Packages offered: TSSOP8 and HWSON8
Table 1. Ordering information Tamb +85 C. Type number PCA9617ADP PCA9617ATP Topside mark P617A P7A Package Name TSSOP8 HWSON8 Description plastic thin shrink small outline package; 8 leads; body width 3 mm plastic thermal enhanced very thin small outline package; no leads; 8 terminals; body 0.8 mm Version SOT505-1 SOT1069-2
Table 2. Ordering options Orderable part number PCA9617ADPJ PCA9617ATPZ Package Packing method Minimum order quantity 2500 4000 Temperature range Type numberReel 13" Q1/T1 *standard mark SMD Reel 7" Q2/T3 *standard mark
All information provided in this document is subject to legal disclaimers.
- Voltage level translation
- Footprint and functional replacement for PCA9517A at fast-mode speeds
- Active high repeater enable input referenced to VCC(B)
- Open-drain input/outputs
- Latching free operation
- Supports arbitration and clock stretching across the repeater
- Powered-OFF high-impedance I²C-bus pins
- Latch-up testing is done to JEDEC Standard JESD78 which exceeds 100mA
- I2C Bus Repeater
- Propagation Delay Time
- 76 ns
- Supply Voltage Max
- 5.5 V
- Supply Voltage Min
- 0.8 V
- Maximum Operating Temperature
- + 85 C
- Mounting Style
- Package / Case
- Maximum Power Dissipation
- 100 mW
- Minimum Operating Temperature
- - 40 C
- Output Type
- Open Drain
- Supply Current
- 8 uA
PCA9617A NXP Technical Data
PCA9617ATPZ Related Products
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1.We provide 90 days warranty.
2.If some of the items you received aren't of perfect quality, we would resiponsibly arrange your refund or replacement. But the items must remain their orginal condition.
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