MPC8349EA PowerQUICC II Pro
- Manufacturer :
- Motorola Semiconductor Products
- Product Categories :
- Microcontrollers , 32 bit
- MPC8349EA PDF
- RoHs Status:
- Lead free / RoHS Compliant
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MPC8349EA Product Details
MPC8349EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications The MPC8349EA PowerQUICC II Pro is a next generation PowerQUICC II integrated host processor. The MPC8349EA contains a processor core built on Power Architecture� technology with system logic for networking, storage, and general-purpose embedded applications. For functional characteristics of the processor, refer to the MPC8349EA PowerQUICC II Pro Integrated Host Processor Family Reference Manual.MPC8349EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications
The MPC8349EA PowerQUICC II Pro is a next generation PowerQUICC II integrated host processor. The MPC8349EA contains a processor core built on Power Architecture� technology with system logic for networking, storage, and general-purpose embedded applications. For functional characteristics of the processor, refer to the MPC8349EA PowerQUICC II Pro Integrated Host Processor Family Reference Manual. To locate published errata or updates for this document, refer to the MPC8349EA product summary page on our website, as listed on the back cover of this document, or contact your local Freescale sales office.
Contents Overview. 2 Electrical Characteristics. 6 Power Characteristics. 10 Clock Input Timing. 12 RESET Initialization. 13 DDR and DDR2 SDRAM. 15 DUART. 21 Ethernet: Three-Speed Ethernet, MII Management. 22 USB. 34 Local Bus. 35 JTAG. I2C. 45 PCI. 47 Timers. 49 GPIO. 50 IPIC. 51 SPI. 52 Package and Pin Listings. 53 Clocking. 66 Thermal. 74 System Design Information. 79 Ordering Information. 82 Document Revision History. 84
NOTE The information in this document is accurate for revision 3.x silicon and later (in other words, for orderable part numbers ending A or B). For information on revision 1.1 silicon and earlier versions, see the MPC8349E PowerQUICC II Pro Integrated Host Processor Hardware Specifications. See Section 22.1, "Part Numbers Fully Addressed by This Document," for silicon revision level determination.
This section provides a high-level overview of the device features. Figure 1 shows the major functional units within the MPC8349EA.
DDR/DD R2 ROM SDRAM IRQs DDR/DDR2 Memory Controller Local Bus Controller Programmable Interrupt Controller Security Engine SPI Serial USB0 USB1 GPIO I Serial Peripheral Interface DUARTMII, GMII, TBI, RTBI, RGMII MII, GMII, TBI, RTBI, RGMII
Major features of the device are as follows: Embedded PowerPC e300 processor core; operates to 667 MHz High-performance, superscalar processor core Floating-point, integer, load/store, system register, and branch processing units 32-Kbyte instruction cache, 32-Kbyte data cache Lockable portion of L1 cache Dynamic power management Software-compatible with the other Freescale processor families that implement Power Architecture technology
MPC8349EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 12 2 Freescale Semiconductor
Double data rate, DDR1/DDR2 SDRAM memory controller Programmable timing supporting DDR1 and DDR2 SDRAM or 64-bit data interface, to 400 MHz data rate Up to four physical banks (chip selects), each bank to 1 Gbyte independently addressable DRAM chip configurations from 64 Mbits to 1 Gbit with �8/�16 data ports Full error checking and correction (ECC) support Support for to 16 simultaneous open pages (up to 32 pages for DDR2) Contiguous or discontiguous memory mapping Read-modify-write support Sleep-mode support for SDRAM self refresh Auto refresh On-the-fly power management using CKE Registered DIMM support 2.5-V SSTL2 compatible I/O for 1.8-V SSTL2 compatible I/O for DDR2 Dual three-speed (10/100/1000) Ethernet controllers (TSECs) Dual controllers designed to comply with IEEE 802.3zTM, 802.3acTM standards Ethernet physical interfaces: � 1000 Mbps IEEE Std. 802.3 GMII/RGMII, IEEE Std. 802.3z TBI/RTBI, full-duplex � 10/100 Mbps IEEE Std. 802.3 MII full- and half-duplex Buffer descriptors are backward-compatible with MPC8260 and MPC860T 10/100 programming models 9.6-Kbyte jumbo frame support RMON statistics support Internal 2-Kbyte transmit and 2-Kbyte receive FIFOs per TSEC module MII management interface for control and status Programmable CRC generation and checking Dual PCI interfaces Designed to comply with PCI Specification Revision 2.3 Data bus width options: � Dual 32-bit data PCI interfaces operating to 66 MHz � Single 64-bit data PCI interface operating to 66 MHz PCI 3.3-V compatible PCI host bridge capabilities on both interfaces PCI agent mode on PCI1 interface PCI-to-memory and memory-to-PCI streaming Memory prefetching of PCI read accesses and support for delayed read transactions Posting of processor-to-PCI and PCI-to-memory writesMPC8349EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 12
|Manufacturer||Motorola Semiconductor Products||RoHs Status||Lead free / RoHS Compliant|
|Packing||Tape & Reel (TR)/Cut Tape (CT)/Tray/Tube||Package/Case|
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