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MPC561/MPC562 / MPC563/MPC564 RISC MCU Including Peripheral Pin Multiplexing with Flash and Code Compression Options

  • Package/Case :
  • BGA
  • Product Categories :
  • Processors and Microcontrollers ; Legacy MCU/MPUs ; 5xx Controllers;
  • RoHs Status:
  • Lead free / RoHS Compliant
  • In-stock:
  • 232


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MPC563MZP56B Product Details


The MPC561/MPC562 / MPC563/MPC564 are members of the Motorola MPC500 RISC Microcontroller
family. As shown in the block diagram, they are composed of:
• High performance CPU system
— High performance core
• Single issue integer core
• Compatible with PowerPC instruction set architecture
• Precise exception model
• Floating point
• Extensive system development support
— On-chip watchpoints and breakpoints
— Program flow tracking
— Background debug mode (BDM)
— IEEE-ISTO Nexus 5001-1999 Class 3 Debug Interface
— MPC500 system interface (USIU, BBC, L2U)
— Fully static design
— Four major power saving modes
• On, doze, sleep, deep-sleep and power-down
— 32-Kbyte static RAM (CALRAM)
— 512-Kbyte flash (UC3F) on MPC563/MPC564
— General-purpose I/O support
• On address (24) and data (32) pins
• 16 GPIO in MIOS14
• Many peripheral pins can be used as GPIO when not used as primary functions
• 2.6-V outputs on external bus pins
• PPM (peripheral pin multiplexing with parallel-to-serial driver) module
• Available in package or die
— Plastic ball grid array (PBGA) packaging
    Key Feature Details
   MPC500 System Interface (USIU)
• System configuration and protection features:
— Periodic-interrupt timer
— Bus monitor
— Software watchdog timer

— Real-time clock (RTC)

— Decrementer
— Time base
• Clock synthesizer
• Power management
• Reset controller
• External bus interface that tolerates 5-V inputs, provides 2.6-V outputs and supports multiple-master
• Enhanced interrupt controller that supports up to eight external and 40 internal interrupts, simplifies
   the interrupt structure and decreases interrupt processing time
• USIU supports dual mapping to map part of one internal/external memory to another external
• USIU supports dual mapping of flash on MPC563MZP56B and MPC564 to move part of internal flash memory
   to external bus for development
• External bus, supporting non-wraparound burst for instruction fetches, with up to 8 instructions per
   memory cycle
   Burst Buffer Controller (BBC) Module
• Support for enhanced interrupt controller (EIC)
• Support for enhanced exception table relocation feature
• Branch target buffer
• Contains 2-Kbytes of decompression RAM (DECRAM) for code compression. This RAM may also
   be used as general-purpose RAM when code compression feature not used.
   Flexible Memory Protection Unit
• Flexible memory protection units (MPU) in BBC and L2U
• Default attributes available in one global entry
• Attribute support for speculative accesses
• Up to eight memory regions are supported, four for data and four for instructions
Memory Controller
• Four flexible chip selects via memory controller
• 24-bit address and 32-bit data buses
• 4-Kbyte to one 16-Mbyte (data) or four-Gbyte (instruction) region size support
• Supports enhanced external burst
• Up to eight-beat transfer bursts, two-clock minimum bus transactions
• Use with SRAM, EPROM, flash and other peripherals
• Byte selects or write enables
• 32-bit address decodes with bit masks
• Four regions
   512-Kbytes of CDR3 Flash EEPROM Memory (UC3F) – MPC563MZP56B Only
• One 512-Kbyte module
• Page read mode
• Block (64 Kbytes) erasable
• External 4.75- to 5.25-V VFLASH power supply for program, erase, and read operations
   32-Kbyte static RAM (CALRAM)
• Composed of one 32-Kbyte CALRAM module
— 28-Kbyte static RAM
— 4-Kbyte calibration (overlay) RAM feature that allows calibration of flash-based constants
• Eight 512-byte overlay regions
• One clock fast accesses
• Two-clock cycle access option for power saving
• Keep-alive power (VDDSRAM) for data retention



  • 512 KB of flash
  • Precise exception model
  • Floating point
  • Extensive system development support
  • On-chip watchpoints and breakpoints
  • Background debug mode (BDM)
  • IEEE®-ISTO 5001-1999 NEXUS class 3 debug interface
  • True 5-volt I/O
  • Two time processing units (TPU3) with 8 KB DPTRAM
  • 22-channel MIOS timer (MIOS14)
  • Two queued analog-to-digital converter modules (QADC64_A, QADC64_B) providing a total of 32 analog channels
  • Three TouCAN modules (TOUCAN_A, TOUCAN_B, TOUCAN_C)
  • One queued serial module with one queued SPI and two SCIs (QSMCM) 32 KB static RAM (CALRAM)

MPC563MZP56B Block Diagram
(Picture: Diagram)

Technical Parameters

  • Manufacturer
  • Packing
  • Tape & Reel (TR)/Cut Tape (CT)/Tray/Tube
  • RoHs Status
  • Lead free / RoHS Compliant
  • Package/Case
  • BGA

MPC563MZP56B Documents

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Ratings and Reviews (3)

  • 5 / 5
  • 5 Stars 100%
  • 4 Stars 0%
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  • 2 Stars 0%
  • 1 Stars 0%
  • **lexa***

    quality ok ,delivery ok

  • **orld***

    Arrived quickly, as described, great stuff!

  • **abri***

    Muchas gracias por la rapidez. Vendedor excelente y cumplidor. Lo recomiendo!!!!

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Estimated Delivery Time: Aug 24 - Aug 29 days (choose Expedited at checkout).

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1.We provide 90 days warranty.

2.If some of the items you received aren't of perfect quality, we would resiponsibly arrange your refund or replacement. But the items must remain their orginal condition.


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(1)Such as a deficiency in quantity, delivery of wrong items, and apparent external defects (breakage and rust, etc.), and we acknowledge such problems.
(2)We are informed of the defect described above within 90 days after the delivery of MPC563MZP56B.
(3)The MPC563MZP56B is unused and only in the original unpacked packaging.
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Freescale Semiconductor, Inc. (NXP Semiconductors)

Freescale Semiconductor, Inc. provides original equipment manufacturers with chips to help them drive advanced cell phones, manage Internet traffic and to help make vehicles safer and more energy efficient. Freescale Semiconductor is the third largest chipmaker in the United States and the ninth lar...

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