The Do-it-All PLD for Low Density Applications
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MACHXO2 Product Details
The MachXO2 family of infinitely reconfigurable Programmable Logic Devices (PLDs) offers designers of low density PLDs an unprecedented mix of low cost, low power and high system integration in a single device. Combining an optimized look-up table (LUT) architecture with 65-nm embedded Flash process technology, the MachXO2 family delivers a 3X increase in logic density, a 10X increase in embedded memory, more than a 100X reduction in static power and up to 30% lower cost compared to the prior generation MachXO PLD family. In addition, the MachXO2 family includes hardened implementations of some of the most popular functions used in system applications (telecom infrastructure, computing, high end industrial, high end medical) and consumer applications (smart phones, GPS devices, mobile computing, digital cameras). These include User Flash Memory (UFM), I2C, SPI and timer/counter. Thus, through the provision of these features and capabilities, the MachXO2 family offers designers a "Do-it-All PLD" for low density applications.Features
Flexible Logic Architecture Ultra Low Power Devices
Advanced 65 nm low power process As low 19 �W standby power Programmable low swing differential I/Os Stand-by mode and other power saving options Six devices with 6864 LUT4s and to 335 I/Os
Eight primary clocks Up to two edge clocks per edge for high-speed I/O interfaces Up to two analog PLLs per device with fractional-n frequency synthesis � Wide input frequency range (10 MHz to 400 MHz)
Instant-on � powers up in microseconds Single-chip, secure solution Programmable through JTAG, SPI or I2C Supports background programming of non-volatile memory Optional dual boot with external SPI memoryto 240 Kbits sysMEMTM Embedded Block RAM to 54 Kbits Distributed RAM Dedicated FIFO control logic
to 256 Kbits of User Flash Memory 100,000 write cycles Accessible through WISHBONE, SPI, I2C and JTAG interfaces Can be used as soft processor PROM or as Flash memoryIn-field logic update while system operates
On-chip hardened functions: SPI, I2C, timer/ counter On-chip oscillator with 5% accuracy Unique TraceID for system tracking One Time Programmable (OTP) mode Single power supply with extended operating range IEEE Standard 1149.1 boundary scan IEEE 1532 compliant in-system programming
DDR registers in I/O cells Dedicated gearing logic 7:1 Gearing for Display I/Os Generic DDR, DDRX2, DDRX4 Dedicated DDR/DDR2/LPDDR memory with DQS support
TQFP, WLCSP, ucBGA, csBGA, caBGA, ftBGA, fpBGA package options Small footprint package options � As small as 2.5x2.5mm Density migration supported Advanced halogen-free packaging
Programmable sysIOTM buffer supports wide range of interfaces: � LVCMOS 3.3/2.5/1.8/1.5/1.2 � LVTTL � PCI � LVDS, Bus-LVDS, MLVDS, RSDS, LVPECL � SSTL 25/18 � HSTL 18 � Schmitt trigger inputs, to 0.5V hysteresis I/Os support hot socketing On-chip differential termination Programmable pull-up or pull-down mode
� 2010 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
Device LUTs Distributed RAM (Kbits) EBR SRAM (Kbits) Number of EBR SRAM Blocks (9 Kbits/block) UFM Memory Bits (Kbits) LCMXO2-640 LCMXO2-1200
VCC Voltage and Device Low Power without Regulator (ZE) � 1.2V Options High Performance with Regulator (HC) 2.5V, 3.3V Number of PLLs Hardened Functions: I2C SPI Timer/Counter Packages 25-ball WLCSP (2.5x2.5 mm, 0.4 mm) 36-ball WLCSP (3.1x3.1 mm, 0.4 mm) 64-ball ucBGA (4x4 mm, 0.4 mm) 100-pin TQFP (14x14 mm, 0.5 mm) 132-ball csBGA (8x8 mm, 0.5 mm) 144-pin TQFP (20x20 mm, 0.5 mm) 256-ball caBGA (14x14 mm, 0.8 mm) 256-ball ftBGA (17x17 mm, 1.0 mm) 332-ball caBGA (17x17 mm, 0.8 mm) 484-ball fpBGA (23x23 mm, 1.0 mm)
Notes: Common footprint allows density migration within the same package. 1. Contact your Lattice sales representative for the support of WLCSP packages.
Low Power without Regulator (ZE) � 1.2V High Performance with Regulator (HC) 2.5V, 3.3V High Performance without Regulator (HE) � 1.2V I/Os
The MachXO2 family of ultra low power, instant-on, non-volatile PLDs has six devices with densities ranging from to 6864 Look-Up Tables (LUTs). In addition to LUT-based, low-cost programmable logic these devices feature Embedded Block RAM (EBR), Distributed RAM, User Flash Memory (UFM), Phase Locked Loops (PLLs), preengineered source synchronous I/O support, advanced configuration support including dual-boot capability and hardened versions of commonly used functions such as SPI controller, I2C controller and timer/counter. These features allow these devices to be used in low cost, high volume consumer and system applications. The MachXO2 devices are designed a 65nm non-volatile low power process. The device architecture has several features such as programmable low swing differential I/Os and the ability to turn off I/O banks, on-chip PLLs and oscillators dynamically. These features help manage static and dynamic power consumption resulting in low microwatt static power for all members of the family. The MachXO2 devices are available in two versions � ultra low power (ZE) and high performance (HC and HE) devices. The ultra low power devices are offered in three speed grades -1, -2 and -3, with -3 being the fastest. Similarly, the high-performance devices are offered in three speed grades: -4, -5 and -6, with -6 being the fastest. HC devices have an internal linear voltage regulator which supports external VCC supply voltages ZE 1-2
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1.We provide 90 days warranty.
2.If some of the items you received aren't of perfect quality, we would resiponsibly arrange your refund or replacement. But the items must remain their orginal condition.
- Q: How does Jotrin guarantee that MACHXO2 is the original manufacturer or agent of Lattice?
- We have a professional business development department to strictly test and verify the qualifications of Lattice original manufacturers and agents. All Lattice suppliers must pass the qualification review before they can publish their MACHXO2 devices; we pay more attention to the channels and quality of MACHXO2 products than any other customer. We strictly implement supplier audits, so you can purchase with confidence.
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- Q: Are the Lattice's MACHXO2 price and stock displayed on the platform accurate?
- The Lattice's inventory fluctuates greatly and cannot be updated in time, it will be updated periodically within 24 hours. After submitting an order for MACHXO2, it is recommended to confirm the order with Jotrin salesperson or online customer service before payment.
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Yes. We accept offline orders.
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- Q: What is the process for returns or replacement of MACHXO2?
All goods will implement Pre-Shipment Inspection (PSI), selected at random from all batches of your order to do a systematic inspection before arranging the shipment.
If there is something wrong with the MACHXO2 we delivered, we will accept the replacement or return of the MACHXO2 only when all of the below conditions are fulfilled:
(1)Such as a deficiency in quantity, delivery of wrong items, and apparent external defects (breakage and rust, etc.), and we acknowledge such problems.
(2)We are informed of the defect described above within 90 days after the delivery of MACHXO2.
(3)The MACHXO2 is unused and only in the original unpacked packaging.
Two processes to return the products:
(1)Inform us within 90 days
(2)Obtain Requesting Return Authorizations
More details about return electronic components please see our Return & Change Policy.
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