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LFE3-35EA-8FN484I/C

Name: LFE3-35EA-8FN484I/C
Brand: LATTICE
SKU: JT24-LFE3-35EA-8FN484I/C
Price: 0.0001 USD
Availability: InStock
Rating: 5 (1 reviews)

Manufacturer :	Lattice Semiconductor Corp
Package/Case :	BGA
Product Categories :	LatticeECP3 Family
Datasheet:
RoHs Status:	Lead free/RoHS Compliant
In-stock:	261

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LFE3-35EA-8FN484I/C Product Details

The LatticeECP3™ (EConomy Plus Third generation) family of FPGA devices is optimized to deliver high performance features such as an enhanced DSP architecture, high speed SERDES and high speed source synchronous interfaces in an economical FPGA fabric. This combination is achieved through advances in device architecture and the use of 65 nm technology making the devices suitable for high-volume, high-speed, low-cost applications.

The LatticeECP3 device family expands look-up-table (LUT) capacity to 149K logic elements and supports up to 586 user I/Os. The LatticeECP3 device family also offers up to 320 18 x 18 multipliers and a wide range of parallel I/O standards.

The LatticeECP3 FPGA fabric is optimized with high performance and low cost in mind. The LatticeECP3 devices utilize reconfigurable SRAM logic technology and provide popular building blocks such as LUT-based logic, distributed and embedded memory, Phase Locked Loops (PLLs), Delay Locked Loops (DLLs), pre-engineered source synchronous I/O support, enhanced sysDSP slices and advanced configuration support, including encryption and dual-boot capabilities.

The pre-engineered source synchronous logic implemented in the LatticeECP3 device family supports a broad range of interface standards, including DDR3, XGMII and 7:1 LVDS.

The LatticeECP3 device family also features high speed SERDES with dedicated PCS functions. High jitter tolerance and low transmit jitter allow the SERDES plus PCS blocks to be configured to support an array of popular data protocols including PCI Express, SMPTE, Ethernet (XAUI, GbE, and SGMII) and CPRI. Transmit Pre-emphasis and Receive Equalization settings make the SERDES suitable for transmission and reception over various forms of media.

The LatticeECP3 devices also provide flexible, reliable and secure configuration options, such as dual-boot capability, bit-stream encryption, and TransFR field upgrade features.

The Lattice Diamond™ and ispLEVER® design software allows large complex designs to be efficiently implemented using the LatticeECP3 FPGA family. Synthesis library support for LatticeECP3 is available for popular logic synthesis tools. Diamond and ispLEVER tools use the synthesis tool output along with the constraints from its floor planning tools to place and route the design in the LatticeECP3 device. The tools extract the timing from the routing and back-annotate it into the design for timing verification.

Lattice provides many pre-engineered IP (Intellectual Property) modules for the LatticeECP3 family. By using these configurable soft core IPs as standardized blocks, designers are free to concentrate on the unique aspects of their design, increasing their productivity.

Feature

 Higher Logic Density for Increased System Integration

• 17K to 149K LUTs

• 116 to 586 I/Os  Embedded SERDES

• 150 Mbps to 3.2 Gbps for Generic 8b10b, 10-bit SERDES, and 8-bit SERDES modes

• Data Rates 230 Mbps to 3.2 Gbps per channel for all other protocols

• Up to 16 channels per device: PCI Express, SONET/SDH, Ethernet (1GbE, SGMII, XAUI), CPRI, SMPTE 3G and Serial RapidIO

 sysDSP™

• Fully cascadable slice architecture

• 12 to 160 slices for high performance multiply and accumulate

• Powerful 54-bit ALU operations

• Time Division Multiplexing MAC Sharing

• Rounding and truncation

• Each slice supports

— Half 36x36, two 18x18 or four 9x9 multipliers

— Advanced 18x36 MAC and 18x18 MultiplyMultiply-Accumulate (MMAC) operations

 Flexible Memory Resources

• Up to 6.85Mbits sysMEM™ Embedded Block RAM (EBR)

• 36K to 303K bits distributed RAM

 sysCLOCK Analog PLLs and DLLs

• Two DLLs and up to ten PLLs per device

 Pre-Engineered Source Synchronous I/O

• DDR registers in I/O cells

• Dedicated read/write levelling functionality

• Dedicated gearing logic

• Source synchronous standards support

— ADC/DAC, 7:1 LVDS, XGMII

— High Speed ADC/DAC devices

• Dedicated DDR/DDR2/DDR3 memory with DQS support

• Optional Inter-Symbol Interference (ISI) correction on outputs

 Programmable sysI/O™ Buffer Supports Wide Range of Interfaces

• On-chip termination

• Optional equalization filter on inputs

• LVTTL and LVCMOS 33/25/18/15/12

• SSTL 33/25/18/15 I, II

• HSTL15 I and HSTL18 I, II

• PCI and Differential HSTL, SSTL

• LVDS, Bus-LVDS, LVPECL, RSDS, MLVDS

 Flexible Device Configuration

• Dedicated bank for configuration I/Os

• SPI boot flash interface

• Dual-boot images supported

• Slave SPI

• TransFR™ I/O for simple field updates

• Soft Error Detect embedded macro

 System Level Support

• IEEE 1149.1 and IEEE 1532 compliant

• Reveal Logic Analyzer

• ORCAstra FPGA configuration utility

• On-chip oscillator for initialization & general use

• 1.2 V core power supply

LFE3-35EA-8FN484I/C Block Diagram
(Picture: Diagram)

Technical Parameters

Manufacturer
LATTICE
Packing
Tape & Reel (TR)/Cut Tape (CT)/Tray/Tube
RoHs Status
Lead free/RoHS Compliant
Package/Case
BGA

LFE3-35EA-8FN484I/C Datasheet

LFE3-35

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Ratings and Reviews (1)

5 / 5

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2 Stars 0%
1 Stars 0%

**as T***

2020-01-08

Excelente refacciones lo recomiendo

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2.If some of the items you received aren't of perfect quality, we would resiponsibly arrange your refund or replacement. But the items must remain their orginal condition.

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Q: How does Jotrin guarantee that LFE3-35EA-8FN484I/C is the original manufacturer or agent of LATTICE?: We have a professional business development department to strictly test and verify the qualifications of LATTICE original manufacturers and agents. All LATTICE suppliers must pass the qualification review before they can publish their LFE3-35EA-8FN484I/C devices; we pay more attention to the channels and quality of LFE3-35EA-8FN484I/C products than any other customer. We strictly implement supplier audits, so you can purchase with confidence.
Q: How to find the detailed information of LFE3-35EA-8FN484I/C chips? Including LATTICE original factory information, LatticeECP3 Family application, LFE3-35EA-8FN484I/C pictures?: You can use Jotrin's intelligent search engine, or filter by LatticeECP3 Family category, or find it through Lattice Semiconductor Corp Information page.
Q: Are the LATTICE's LFE3-35EA-8FN484I/C price and stock displayed on the platform accurate?: The LATTICE's inventory fluctuates greatly and cannot be updated in time, it will be updated periodically within 24 hours. After submitting an order for LFE3-35EA-8FN484I/C, it is recommended to confirm the order with Jotrin salesperson or online customer service before payment.
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Q: What is the process for returns or replacement of LFE3-35EA-8FN484I/C?: All goods will implement Pre-Shipment Inspection (PSI), selected at random from all batches of your order to do a systematic inspection before arranging the shipment. If there is something wrong with the LFE335EA8FN484IC we delivered, we will accept the replacement or return of the LFE3-35EA-8FN484I/C only when all of the below conditions are fulfilled:
(1)Such as a deficiency in quantity, delivery of wrong items, and apparent external defects (breakage and rust, etc.), and we acknowledge such problems.
(2)We are informed of the defect described above within 90 days after the delivery of LFE3-35EA-8FN484I/C.
(3)The LFE3-35EA-8FN484I/C is unused and only in the original unpacked packaging.
Two processes to return the products:
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More details about return electronic components please see our Return & Change Policy.
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Lattice Semiconductor Corp

Lattice Semiconductor Corporation is a leading provider of Programmable Logic Devices, software, Intellectual Property, and development kits. The Mid-Range Lattice ECP3 family is the lowest power SerDes enabled FPGA available in the market. The MachXO is the most versatile non-volatile PLD targeted...