10/100 Non-PCI Ethernet Single Chip MAC + PHY
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LAN91C111I-NE Product Details
The Microchip LAN91C111I-NE is designed to facilitate the implementation of a third generation of Fast Ethernet connectivity solutions for embedded applications. For this third generation of products, flexibility and integration dominate the design requirements. The LAN91C111I-NE is a mixed signal Analog/Digital device that implements the MAC and PHY portion of the CSMA/CD protocol at 10 and 100 Mbps. The design will also minimize data throughput constraints utilizing a 32-bit, 16-bit or 8-bit bus Host interface in embedded applications. The total internal memory FIFO buffer size is 8 Kbytes, which is the total chip storage for transmit and receive operations.
The Microchip LAN91C111I-NE is software compatible with the LAN9000 family of products.
Memory management is handled using a patented optimized MMU (Memory Management Unit) architecture and a 32-bit wide internal data path. This I/O mapped architecture can sustain back-to- frame transmission and reception for superior data throughput and optimal performance. It also dynamically allocates buffer memory in an efficient buffer utilization scheme, reducing software tasks and relieving the host CPU from performing these housekeeping functions.
The Microchip LAN91C111I-NE provides a flexible slave interface for easy connectivity with industry-standard buses. The Bus Interface Unit (BIU) can handle synchronous as well as asynchronous transfers, with different signals being used for each one. Asynchronous bus support for ISA is supported even though ISA cannot sustain 100 Mbps traffic. Fast Ethernet data rates are attainable for ISA-based nodes on the basis of the aggregate traffic benefits.
Two different interfaces are supported on the network side. The first Interface is a standard Magnetics transmit/receive pair interfacing to 10/100Base-T utilizing the internal physical layer block. The second interface follows the MII (Media Independent Interface) specification standard, consisting of 4 bit wide data transfers at the nibble rate. This interface is applicable to 10 Mbps standard Ethernet or 100 Mbps Ethernet networks. Three of the LAN91C111’s pins are used to interface to the two-line MII serial management protocol.
The Microchip LAN91C111I-NE integrates IEEE 802.3 Physical Layer for twisted pair Ethernet applications. The PHY can be configured for either 100 Mbps (100Base-TX) or 10 Mbps (10Base-T) Ethernet operation. The Analog PHY block consists of a 4B5B/Manchester encoder/decoder, scrambler/de-scrambler, transmitter with wave shaping and output driver, twisted pair receiver with on chip equalizer and baseline wander correction, clock and data recovery, Auto-Negotiation, controller interface (MII), and serial port (MI). Internal output wave shaping circuitry and on-chip filters eliminate the need for external filters normally required in 100Base-TX and 10Base-T applications.
The LAN91C111I-NE can automatically configure itself for 100 or 10 Mbps and Full or Half Duplex operation with the on-chip Auto-Negotiation algorithm. The LAN91C111I-NE is ideal for media interfaces for embedded application desiring Ethernet connectivity as well as 100Base-TX/10Base-T adapter cards, motherboards, repeaters, switching hubs. The LAN91C111I-NE operates from a single 3.3V
- Single Chip Ethernet Controller
- Dual Speed - 10/100 Mbps
- Fully Supports Full Duplex Switched Ethernet
- Supports Burst Data Transfer
- 8 Kbytes Internal Memory for Receive and Transmit FIFO Buffers
- Enhanced Power Management Features
- Optional Configuration via Serial EEPROM Interface
- Supports 8, 16 and 32 Bit CPU Accesses
- Internal 32 Bit Wide Data Path (into Packet Buffer Memory)
- Built-in Transparent Arbitration for Slave Sequential Access Architecture
- Flat MMU Architecture with Symmetric Transmit and Receive Structures and Queues
- 3.3V Operation with 5V Tolerant I/O Buffers
- Single 25 MHz Reference Clock for Both PHY and MAC
- External 25 MHz Output Pin for an External PHY Supporting PHY's Physical Media
- Low Power CMOS Design
- Supports Multiple Embedded Processor Host Interfaces
- Power PC
- 680X0, 683XX
- MIPS R3000
- 3.3V MII (Media Independent Interface) MAC-PHY Interface Running at Nibble Rate
- MII Management Serial Interface
- 128 Pin QFP RoHS compliant package
- 128 Pin TQFP 1.0 mm height RoHS compliant package
- Commercial Temperature Range from 0°C to 70°C (LAN91C111)
- Industrial Temperature Range from -40°C to 85°C (LAN91C111i)
- Fully Integrated IEEE 802.3/802.3u - 100BASE-TX/10BASE-T Physical Layer
- Auto Negotiation: 10/100, Full/Half Duplex
- On Chip Wave Shaping - No External Filters Required
- Adaptive Equalizer
- Baseline Wander Correction
- LED Outputs (User Selectable - Up to Two LED Functions at One Time)
- Full Duplex
- Ethernet Controllers
- Number of Transceivers
- Data Rate
- 10 Mb/s, 100 Mb/s
- Supply Voltage Max
- 5 V
- Supply Voltage Min
- 0 V
- Maximum Operating Temperature
- + 85 C
- Package / Case
- Ethernet Connection Type
- 10 Base-T, 100 Base-TX
- Maximum Supply Current
- 140 mA
- Minimum Operating Temperature
- - 40 C
- Mounting Style
- Factory Pack Quantity
- Standard Supported
- 802.3, 802.3u
- Single Chip MAC and PHY
LAN91C111I-NE Related Products
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Estimated Delivery Time: Jul 10 - Jul 15 days (choose Expedited at checkout).
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1.We provide 90 days warranty.
2.If some of the items you received aren't of perfect quality, we would resiponsibly arrange your refund or replacement. But the items must remain their orginal condition.
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- We have a professional business development department to strictly test and verify the qualifications of MICROCHIP original manufacturers and agents. All MICROCHIP suppliers must pass the qualification review before they can publish their LAN91C111I-NE devices; we pay more attention to the channels and quality of LAN91C111I-NE products than any other customer. We strictly implement supplier audits, so you can purchase with confidence.
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- You can use Jotrin's intelligent search engine, or filter by Ethernet Controller Products category, or find it through Microchip Technology, Inc Information page.
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- The MICROCHIP's inventory fluctuates greatly and cannot be updated in time, it will be updated periodically within 24 hours. After submitting an order for LAN91C111I-NE, it is recommended to confirm the order with Jotrin salesperson or online customer service before payment.
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- Q: What is the process for returns or replacement of LAN91C111I-NE?
All goods will implement Pre-Shipment Inspection (PSI), selected at random from all batches of your order to do a systematic inspection before arranging the shipment.
If there is something wrong with the LAN91C111INE we delivered, we will accept the replacement or return of the LAN91C111I-NE only when all of the below conditions are fulfilled:
(1)Such as a deficiency in quantity, delivery of wrong items, and apparent external defects (breakage and rust, etc.), and we acknowledge such problems.
(2)We are informed of the defect described above within 90 days after the delivery of LAN91C111I-NE.
(3)The LAN91C111I-NE is unused and only in the original unpacked packaging.
Two processes to return the products:
(1)Inform us within 90 days
(2)Obtain Requesting Return Authorizations
More details about return electronic components please see our Return & Change Policy.
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