Products > Integrated Circuits (ICs) > Clock & Timer ICs > HMC7044LP10BE

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Clock Multiplier, Jitter Attenuator, 3.2 GHz, 14 Outputs, 3.135 V to 3.465 V supply, LFCSP-68

  • Package/Case :
  • QFN-68
  • Product Categories :
  • Clock Generators, PLLs, Frequency Synthesizers
  • RoHs Status:
  • Green
  • In-stock:
  • 105


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HMC7044LP10BE Product Details

The HMC7044LP10BE is a high performance, dual-loop, integer-N jitter attenuator capable of performing reference selection and generation of ultralow phase noise frequencies for high speed data converters with either parallel or serial (JESD204B/JESD204C type) interfaces. The HMC7044LP10BE features two integer mode PLLs and overlapping on-chip VCOs that are SPI-selectable with wide tuning ranges around 2.5 GHz and 3 GHz, respectively. The device is designed to meet the requirements of GSM and LTE base station designs, and offers a wide range of clock management and distribution features to simplify baseband and radio card clock tree designs. The HMC7044LP10BE provides 14 low noise and configurable outputs to offer flexibility in interfacing with many different components including data converters, field-programmable gate arrays (FPGAs), and mixer local oscillators (LOs).

The DCLK and SYSREF clock outputs of the HMC7044LP10BE can be configured to support signaling standards, such as CML, LVDS, LVPECL, and LVCMOS, and different bias settings to offset varying board insertion losses.


  • Ultralow rms jitter: 44 fs typical (12 kHz to 20 MHz) at 2457.6 MHz
  • Noise floor: −156 dBc/Hz at 2457.6 MHz
  • Low phase noise: −141.7 dBc/Hz at 800 kHz, 983.04 MHz output
  • Up to 14 LVDS, LVPECL, or CML type device clocks (DCLKs) from PLL2
    • Maximum CLKOUTx/CLKOUTx and SCLKOUTx/SCLKOUTx frequency up to 3200 MHz
  • JESD204B/JESD204C-compatible system reference (SYSREF) pulses
  • 25 ps analog, and ½ VCO cycle digital delay independently programmable on each of 14 clock output channels
  • SPI-programmable phase noise vs. power consumption
  • SYSREF valid interrupt to simplify JESD204B/JESD204C synchronization
  • Narrow-band, dual core VCOs
  • Up to 2 buffered voltage controlled oscillator (VCXO) outputs
  • Up to 4 input clocks in LVDS, LVPECL, CMOS, and CML modes
  • Frequency holdover mode to maintain output frequency
  • Loss of signal (LOS) detection and hitless reference switching
  • 4× GPIOs alarms/status indicators to determine the health of the system
  • External VCO input to support up to 6000 MHz
  • On-board regulators for excellent PSRR
  • 68-lead, 10 mm × 10 mm LFCSP package


  • JESD204B/JESD204C clock generation
  • Cellular infrastructure (multicarrier GSM, LTE, W-CDMA)
  • Data converter clocking
  • Microwave baseband cards
  • Phase array reference distribution

HMC7044LP10BE Pinout
(Picture: Pinout)

HMC7044LP10BE Block Diagram
(Picture: Diagram)

Technical Parameters

  • Frequency
  • 3.20 GHz
  • Supply Voltage (DC)
  • 3.13 V (min)
  • Product Lifecycle Status
  • Active
  • Packaging
  • Cut Tape (CT)
  • Number of Pins
  • 68
  • Case/Package
  • RoHS
  • Compliant
  • Lead Free Status
  • Contains Lead
  • ECCN Code
  • EAR99

HMC7044LP10BE Documents

  • HMC7044 Technical Documentation/Data sheet

HMC7044LP10BE Related Products

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Analog Devices, Inc. was founded by two MIT graduates, Ray Stata and Matthew Lorber in 1965. The same year, the company released its first product, the model 101 op amp, which was a hockey-puck sized module used in test and measurement equipment. In 1967, the company published the first issue of its...
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