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HMC7043LP7FETR

IC FRACT-N PLL W/SWEEPR 24QFN

  • Package/Case :
  • 48-VFQFN, CSP
  • Product Categories :
  • Clock Generation & Distribution ; Clock Distribution Devices
  • RoHs Status:
  • Pb-free Halide free
  • In-stock:
  • 750

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HMC7043LP7FETR Product Details

The HMC7043LP7FETR is designed to meet the requirements of multicarrier GSM and LTE base station designs, and offers a wide range of clock management and distribution features to simplify baseband and radio card clock tree designs.

The HMC7043LP7FETR provides 14 low noise and configurable outputs to offer flexibility in interfacing with many different components in a base transceiver station (BTS) system, such as data converters, local oscillators, transmit/receive modules, field programmable gate arrays (FPGAs), and digital front-end ASICs. The HMC7043LP7FETR can generate up to seven DCLK and SYSREF clock pairs per the JESD204B/JESD204C interface requirements.

The system designer can generate a lower number of DCLK and SYSREF pairs, and configure the remaining output signal paths for independent phase and frequency. Both the DCLK and SYSREF clock outputs can be configured to support different signaling standards, including CML, LVDS, LVPECL, and LVCMOS, and different bias conditions to adjust for varying board insertion losses.

One of the unique features of the HMC7043LP7FETR is the independent flexible phase management of each of the 14 channels. All 14 channels feature both frequency and phase adjustment. The outputs can also be programmed for 50 Ω or 100 Ω internal and external termination options.

The HMC7043LP7FETR device features an RF SYNC feature that synchronizes multiple HMC7043LP7FETR devices deterministically, that is, ensures that all clock outputs start with the same edge. This operation is achieved by rephrasing the nested HMC7043LP7FETR or SYSREF control unit/divider, deterministically, and then restarting the output dividers with this new phase.

The HMC7043LP7FETR is offered in a 48-lead, 7 mm × 7 mm LFCSP package with an exposed pad connected to ground.

Feature

  • JEDEC JESD204B/JESD204C support
  • Low additive jitter: <15 fs rms at 2457.6 MHz (12 kHz to 20 MHz)
  • Very low noise floor: −155.2 dBc/Hz at 983.04 MHz
  • Up to 14 LVDS, LVPECL, or CML type device clocks (DCLKs)
    • Maximum CLKOUTx/CLKOUTx and SCLKOUTx/SCLKOUTx frequency of 3200 MHz
    • JESD204B/JESD204C-compatible system reference (SYSREF) pulses
    • 25 ps analog and ½ clock input cycle digital delay independently programmable on each of 14 clock output channels
  • SPI-programmable adjustable noise floor vs. power consumption
  • SYSREF valid interrupt to simplify JESD204B/JESD204C synchronization
  • Supports deterministic synchronization of multiple HMC7043 devices
  • RFSYNC pin or SPI-controlled SYNC trigger for output synchronization of JESD204B/JESD204C
  • GPIO alarm/status indicator to determine the health of the system
  • Clock input to support up to 6 GHz
  • On-board regulator for excellent PSRR
  • 48-lead, 7 mm × 7 mm LFCSP package

Applications

  • JESD204B/JESD204C clock generation
  • Cellular infrastructure (multicarrier GSM, LTE, W-CDMA)
  • Data converter clocking
  • Phase array reference distribution
  • Microwave baseband cards

HMC7043LP7FETR Pinout
(Picture: Pinout)

HMC7043LP7FETR Block Diagram
(Picture: Diagram)

Technical Parameters

  • Type
  • Clock Buffer
  • PLL
  • Yes
  • Input
  • Clock
  • Output
  • CMOS, LVDS, LVPECL
  • Number of Circuits
  • 1
  • Ratio Input:Output
  • 1:14
  • Differential Input:Output
  • Yes/Yes
  • Frequency Max
  • 3.2GHz
  • Divider/Multiplier
  • Yes/No
  • Voltage Supply
  • 3.135V ~ 3.465V
  • Operating Temperature
  • -40??C ~ 85??C
  • Mounting Type
  • Surface Mount
  • Package / Case
  • 48-VFQFN Exposed Pad, CSP
  • Supplier Device Package
  • 48-LFCSP (7x7)

HMC7043LP7FETR Documents

  • HMC7043 Technical Documentation/Data sheet

HMC7043LP7FETR Related Products

Ratings and Reviews (1)

  • 5 / 5
  • 5 Stars 100%
  • 4 Stars 0%
  • 3 Stars 0%
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  • 1 Stars 0%
  • **anfr***
    2019-08-18

    schon eingebaut und es läuft!

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Analog Devices, Inc

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Analog Devices, Inc. was founded by two MIT graduates, Ray Stata and Matthew Lorber in 1965. The same year, the company released its first product, the model 101 op amp, which was a hockey-puck sized module used in test and measurement equipment. In 1967, the company published the first issue of its...
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