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EP610DI-25

High-performance, 16-macrocell Classic EPLD Pipelined data rates of up to 100 MHz

  • Package/Case :
  • DIP-24
  • Product Categories :
  • Classic EPLD Family
  • RoHs Status:
  • Lead free / RoHS Compliant
  • In-stock:
  • 90

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EP610DI-25 Product Details

The Altera ClassicTM EP610DI-25 device offers a solution to high-speed, lowpower logic integration. Fabricated on advanced CMOS technology, EP610DI-25 devices also have a Turbo-only version, which is described in this data sheet.

Classic devices support 100% TTL emulation and can easily integrate multiple PAL- and GAL-type devices with densities ranging from 300 to 900 usable gates. The Classic family provides pin-to-pin logic delays as low as 10 ns and counter frequencies as high as 100 MHz. Classic devices are available in a wide range of packages, including ceramic dual in-line package (CerDIP), plastic dual in-line package (PDIP), plastic J-lead chip carrier (PLCC), ceramic J-lead chip carrier (JLCC), pin-grid array (PGA), and small-outline integrated circuit (SOIC) packages. 

EP610DI-25 devices have 16 macrocells, 4 dedicated input pins, 16 I/O pins, and 2 global clock pins. Each macrocell can access signals  from the global bus, which consists of the true and complement forms of
the dedicated inputs and the true and complement forms of either the  output of the macrocell or the I/O input. The
CLK1 signal is a dedicated  global clock input for the registers in macrocells 9 through 16. The CLK2 signal is a dedicated global clock input for registers in macrocells 1 through 8.

EPROM-based Classic devices can reduce active power consumption without sacrificing performance. This reduced power consumption makes the Classic family well suited for a wide range of low-power applications. 

Classic devices are 100% generically tested devices in windowed packages and can be erased with ultra-violet (UV) light, allowing design changes to be implemented quickly. Classic devices use sum-of-products logic and a programmable register. The sum-of-products logic provides a programmable-AND/fixed-OR structure that can implement logic with up to eight product terms. The programmable register can be individually programmed for D, T, SR, or JK flipflop operation or can be bypassed for combinatorial operation. In addition, macrocell registers can be individually clocked either by a global clock or by any input or feedback path to the AND array. Altera’s proprietary programmable I/O architecture allows the designer to program output and feedback paths for combinatorial or registered operation in both active-high and active-low modes. These features make it possible to implement a variety of logic functions simultaneously. 

Classic devices are supported by Altera’s MAX+PLUS II development system, a single, integrated package that offers schematic, text—including VHDL, Verilog HDL, and the Altera Hardware Description Language (AHDL)—and waveform design entry, compilation and logic synthesis, simulation and timing analysis, and device programming. The MAX+PLUS II software provides EDIF 2 0 0 and 3 0 0, LPM, VHDL, Verilog HDL, and other interfaces for additional design entry and simulation support from other industry-standard PC- and workstationbased EDA tools. The MAX+PLUS II software runs on Windows-based PCs, as well as Sun SPARCstation, HP 9000 Series 700/800, and IBM RISC System/6000 workstations. These devices also contain on-board logic test circuitry to allow verification of function and AC specifications during standard production flow.

EP610DI-25

Feature

High-performance, 16-macrocell Classic EPLD
– Combinatorial speeds with
tPD as fast as 10 ns
– Counter frequencies of up to 100 MHz
– Pipelined data rates of up to 125 MHz
Programmable I/O architecture with up to 20 inputs or 16 outputs  and 2 clock pins
EP610 and EP610I devices are pin-, function-, and programming file-compatible
Programmable clock option for independent clocking of all registers
Macrocells individually programmable as D, T, JK, or SR flipflops, or  for combinatorial operation
Available in the following packages (see Figure 7):
– 24-pin small-outline integrated circuit (plastic SOIC only)
– 24-pin ceramic and plastic dual in-line package (CerDIP and  PDIP)
– 28-pin plastic J-lead chip carrier (PLCC)
 


EP610DI-25 Pinout
(Picture: Pinout)

EP610DI-25 Block Diagram
(Picture: Diagram)

Technical Parameters

  • Manufacturer
  • ALTERA
  • Packing
  • Tape & Reel (TR)/Cut Tape (CT)/Tray/Tube
  • RoHs Status
  • Lead free / RoHS Compliant
  • Package/Case
  • DIP-24

EP610DI-25 Documents

EP610DI-25 Related Products

Ratings and Reviews (1)

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  • **aidy***
    2020-04-18

    Fantastic! Fast delivery ! Thank you.

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1.We provide 90 days warranty.

2.If some of the items you received aren't of perfect quality, we would resiponsibly arrange your refund or replacement. But the items must remain their orginal condition.

FAQ:

Q: How does Jotrin guarantee that EP610DI-25 is the original manufacturer or agent of ALTERA?
We have a professional business development department to strictly test and verify the qualifications of ALTERA original manufacturers and agents. All ALTERA suppliers must pass the qualification review before they can publish their EP610DI-25 devices; we pay more attention to the channels and quality of EP610DI-25 products than any other customer. We strictly implement supplier audits, so you can purchase with confidence.
Q: How to find the detailed information of EP610DI-25 chips? Including ALTERA original factory information, Classic EPLD Family application, EP610DI-25 pictures?
You can use Jotrin's intelligent search engine, or filter by Classic EPLD Family category, or find it through Altera Corporation (Intel) Information page.
Q: Are the ALTERA's EP610DI-25 price and stock displayed on the platform accurate?
The ALTERA's inventory fluctuates greatly and cannot be updated in time, it will be updated periodically within 24 hours. After submitting an order for EP610DI-25, it is recommended to confirm the order with Jotrin salesperson or online customer service before payment.
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Q: What is the process for returns or replacement of EP610DI-25?
All goods will implement Pre-Shipment Inspection (PSI), selected at random from all batches of your order to do a systematic inspection before arranging the shipment. If there is something wrong with the EP610DI25 we delivered, we will accept the replacement or return of the EP610DI-25 only when all of the below conditions are fulfilled:
(1)Such as a deficiency in quantity, delivery of wrong items, and apparent external defects (breakage and rust, etc.), and we acknowledge such problems.
(2)We are informed of the defect described above within 90 days after the delivery of EP610DI-25.
(3)The EP610DI-25 is unused and only in the original unpacked packaging.
Two processes to return the products:
(1)Inform us within 90 days
(2)Obtain Requesting Return Authorizations
More details about return electronic components please see our Return & Change Policy.
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Altera Corporation (Intel)

Altera
Since inventing the world's first programmable logic device in 1984, Altera Corporation has been providing customers with industry-leading custom logic solutions. Today, we have more than 3,000 employees in 19 countries around the world, and we are providing our customers with more innovative, cust...
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