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EP20K200BC356-3

FPGA - Field Programmable Gate Array CPLD - APEX 20K 832 Macro 277 IOs

  • Package/Case :
  • BGA-356
  • Product Categories :
  • FPGA - Field Programmable Gate Array
  • RoHs Status:
  • Lead free/RoHS Compliant
  • In-stock:
  • 36

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EP20K200BC356-3 Product Details

APEXTM 20K devices are the first PLDs designed with the MultiCore architecture, which combines the strengths of LUT-based and productterm-based devices with an enhanced memory structure. LUT-based logic provides optimized performance and efficiency for data-path, registerintensive, mathematical, or digital signal processing (DSP) designs. Product-term-based logic is optimized for complex combinatorial paths, such as complex state machines. LUT- and product-term-based logic combined with memory functions and a wide variety of MegaCore and AMPP functions make the APEX 20K device architecture uniquely suited for system-on-a-programmable-chip designs. Applications historically requiring a combination of LUT-, product-term-, and memory-based devices can now be integrated into one APEX 20K device.

EP20K200BC356-3

Feature

Industry’s first programmable logic device (PLD) incorporating system-on-a-programmable-chip (SOPC) integration

– MultiCoreTM architecture integrating look-up table (LUT) logic, product-term logic, and embedded memory

– LUT logic used for register-intensive functions

– Embedded system block (ESB) used to implement memory functions, including first-in first-out (FIFO) buffers, dual-port RAM, and content-addressable memory (CAM)

– ESB implementation of product-term logic used for combinatorial-intensive functions

Technical Parameters

  • Series
  • APEX 20K
  • Operating Supply Voltage
  • 2.5 V
  • Maximum Operating Temperature
  • + 70 C
  • Mounting Style
  • SMD/SMT
  • Package / Case
  • BGA-356
  • Minimum Operating Temperature
  • 0 C
  • Packaging
  • Tray

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  • **ewis***
    2020-03-28

    top seller, great item super fast postage many thanks

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