

High-Speed CMOS Logic 14-Stage Binary Counter with Oscillator,Counter Shift Registers 14 Stage Binary
- Manufacturer :
- Texas Instruments, Inc
- Package/Case :
- PDIP-16
- Product Categories :
- Counter Shift Registers
- Datasheet:
- CD74HC4060E PDF
- RoHs Status:
- Rohs
- Marking Code:
- CD74HC4060E
- In-stock:
- 104
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CD74HC4060E Product Details
Data sheet acquired from Harris Semiconductor
DescriptionThe ’HC4060 and ’HCT4060 each consist of an oscillator section and 14 ripple-carry binary counter stages. The oscillator configuration allows design of either RC or crystal oscillator circuits. A Master Reset input is provided which resets the counter to the all-0’s state and disables the oscillator. A high level on the MR line accomplishes the reset function. All counter stages are master-slave flip-flops. The state of the counter is advanced one step in binary order on the negative transition of O). All inputs and outputs are buffered. Schmitt trigger action on the input-pulse-line permits unlimited rise and fall times.
In order to achieve a symmetrical waveform in the oscillator section the HCT4060 input pulse switch points are the same as in the HC4060; only the MR input in the HCT4060 has TTL switching levels.
Feature
- Onboard Oscillator
- Common Reset
- Negative Edge Clocking
- Fanout (Over Temperature Range)
- Standard Outputs . . . . 10 LSTTL Loads
- Bus Driver Outputs . . . . 15 LSTTL Loads
- Wide Operating Temperature Range . . . –55°C to 125°C
- Balanced Propagation Delay and Transition Times
- Significant Power Reduction Compared to LSTTL Logic ICs
- HC Types
- 2V to 6V Operation
- High Noise Immunity: NIL = 30%, NIH = 30% of VCC at VCC = 5V
- HCT Types
- 4.5V to 5.5V Operation
- Direct LSTTL Input Logic Compatibility, VIL = 0.8V (Max), VIH = 2V (Min)
- CMOS Input Compatibility, Il1μA at VOL, VOH
Data sheet acquired from Harris Semiconductor
DescriptionThe ’HC4060 and ’HCT4060 each consist of an oscillator section and 14 ripple-carry binary counter stages. The oscillator configuration allows design of either RC or crystal oscillator circuits. A Master Reset input is provided which resets the counter to the all-0’s state and disables the oscillator. A high level on the MR line accomplishes the reset function. All counter stages are master-slave flip-flops. The state of the counter is advanced one step in binary order on the negative transition of O). All inputs and outputs are buffered. Schmitt trigger action on the input-pulse-line permits unlimited rise and fall times.
In order to achieve a symmetrical waveform in the oscillator section the HCT4060 input pulse switch points are the same as in the HC4060; only the MR input in the HCT4060 has TTL switching levels.
Technical Parameters
Logic Family | CMOS | Packaging | Tube |
---|---|---|---|
Counting Sequence | Up | Mounting Style | Through Hole |
Operating Supply Voltage | 2 V to 6 V | Factory Pack Quantity | 25 |
Package / Case | PDIP-16 |
CD74HC4060E Documents
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CD74HC4060 Family Datasheet
CD74HC4060E Related Products
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