CMOS Quad AND/OR Select Gate 16-TSSOP -55 to 125,Gates (AND / NAND / OR / NOR) CMOS Quad AND/OR Select Gate
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CD4019BPWE4 Product Details
CD4019BPWE4 types consist of four AND/OR select gate configurations, each consisting of two 2-input AND gates driving a single-input OR gate. Selection is accomplished by control bits Ka and Kb. In addition to selection of either channel A or channel B information, the control bits can be applied simultaneously to accomplish the logical A + B function.
The CD4019BPWE4 types are supplied in 16-lead hermetic dual-in-line ceramic packages (F3A suffix),16-lead dual-in-line plastic packages (E suffix), 16-lead small-outline packages (M, M96, MT, and NSR suffixes),and 16-lead thin shrink small-outline packages (PW and PWR suffixes).
- Medium speed operation……tPHL = tPLH = 60 ns (typ.) at CL = 50 pF, VDD = 10 V
- Standardized, symmetrical output characteristics
- 100% tested for quiescent current at 20 V
- 5-V, 10-V, and 15-V parametric ratings
- Meets all requirements of JEDEC Tentative Standard No. 13B, "Standard Specifications for Description of ’B’ Series CMOS Devices"
- Maximum input current of 1 μA at 18 V over full package-temperature range; 100 nA at 18 V and 25°C
- Noise margin (full package-temperature range) =
1 V at VDD = 5 V
2 V at VDD = 10 V
2.5 V at VDD = 15 V
- AND-OR select gating
- Shift-right/shift-left registers
- True/complement selection
- AND/OR/Exclusive-OR selection
|Product||MUX Gates||Maximum Operating Temperature||+ 125 C|
|Logic Family||4000||Mounting Style||SMD/SMT|
|Number of Gates||4||Package / Case||TSSOP-16|
|Number of Lines (Input / Output)||2 / 1||Packaging||Tube|
|High Level Output Current||- 4.2 mA||Minimum Operating Temperature||- 55 C|
|Low Level Output Current||4.2 mA||Number of Input Lines||2|
|Propagation Delay Time||300 ns||Number of Output Lines||1|
|Supply Voltage Max||18 V||Factory Pack Quantity||90|
|Supply Voltage Min||3 V|
CD4019B Family Datasheet
CD4019BPWE4 Related Products
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