ADN4612

The ADN4612 is optimized for nonreturn-to-zero (NRZ) signaling with data rates of up to 11.3 Gbps per port. Each port offers programmable input equalization, loss-of-signal detection, programmable output swing, and output preemphasis/deemphasis. The ADN4612 nonblocking switch core implements a 12 � 12 crossbar and supports independent channel switching through the serial control interface. The ADN4612 has low latency and very low channel-to-channel skew. The ADN4612 is packaged in an 88-lead LFCSP package and operates from −40�C to +85�C. APPLICATIONS Fiber optic network switching 10 Gigabit Ethernet over backplane 10GBASE-KR 802.3ap XLAUI/CAUI (802.3ba) SONET OC-192/STM-64x 1�, 2�, 4�, 8�, and 10� Fibre Channel

to 11.3 Gbps per port, NRZ data rate Multitime constant, programmable receive equalization Compensates 25 inches at 10.3125 Gbps Compensates 15 inches at 11.3 Gbps 6-tap programmable transmit feedforward equalization (FFE) Compensates 15 inches at 10.3125 Gbps Compensates 10 inches at 11.3 Gbps Low power 150 mW per channel 2.5 V (outputs enabled) � 12, fully differential, nonblocking array Double rank connection programming 2-pin selectable connection maps Per lane lost of signal (LOS) detection Flexible output termination supply range 3.3 V) DC- or ac-coupled differential CML inputs and outputs Programmable CML output levels Load from EEPROM for automatic power-on ready operation Per lane input and output P/N pair inversion for routing ease 50 on-chip input/output termination Supports 64-bit/66-bit, scrambled or not coded NRZ data to 11.3 Gbps Serial (I2C or SPI slave) control interface 88-lead LFCSP, � 12 mm, Pb-free package to +85�C operating temperature range

Fiber optic network switching 10 Gigabit Ethernet over backplane 10GBASE-KR 802.3ap XLAUI/CAUI (802.3ba) SONET OC-192/STM-64x and 10� Fibre Channel

The � 12 asynchronous, protocol agnostic, digital crosspoint switch with 12 differential PECL-/CML-compatible inputs and 12 differential CML outputs. The ADN4612 is optimized for nonreturn-to-zero (NRZ) signaling with data rates to 11.3 Gbps per port. Each port provides programmable input equalization, loss of signal (LOS) detection, programmable output swing, and output preemphasis/deemphasis. The ADN4612 nonblocking switch core implements � 12 crossbar and supports independent channel switching through the serial control interface. The ADN4612 has low latency and very low channel-to-channel skew. The ADN4612 is packaged an 88-lead LFCSP package and operates from to +85�C.

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Features.............................................................................................. 1 Applications....................................................................................... 1 Functional Block Diagram.............................................................. 1 General Description......................................................................... 1 Revision History............................................................................... 3 Specifications..................................................................................... 4 Input/Output Specifications........................................................ 4 Power Supply and Thermal Specifications................................ 5 Electrical Specifications--Control Logic Pins.......................... I C Master and Slave Timing Specifications............................. 6

Register Descriptions..................................................................... 47 Software Reset Register............................................................. 47 Tx Enable Control Registers..................................................... 47 Tx Reference Enable Register................................................... 48 Squelch Control Register........................................................... 48 Rx and Tx Swap Sign Registers................................................. 48 XPT Broadcast Lane Number Register.................................... Tx 0 Driver Control Registers.................................................. Tx 0 Driver Enable Registers.................................................... Tx 0 Driver Resolution Registers............................................. Tx 1 Driver Control Registers.................................................. Tx 1 Driver Enable Registers.................................................... Tx 1 Driver Resolution Registers............................................. Tx 2 Driver Control Registers.................................................. Tx 2 Driver Enable Registers.................................................... Tx 2 Driver Resolution Registers............................................. Tx 3 Driver Control Registers.................................................. Tx 3 Driver Enable Registers.................................................... Tx 3 Driver Resolution Registers............................................. Tx 4 Driver Control Registers.................................................. Tx 4 Driver Enable Registers.................................................... Tx 4 Driver Resolution Registers............................................. Tx 5 Driver Control Registers.................................................. Tx 5 Driver Enable Registers.................................................... Tx 5 Driver Resolution Registers............................................. Tx 6 Driver Control Registers.................................................. Tx 6 Driver Enable Registers.................................................... Tx 6 Driver Resolution Registers............................................. Tx 7 Driver Control Registers.................................................. Tx 7 Driver Enable Registers.................................................... Tx 7 Driver Resolution Registers............................................. Tx 8 Driver Control Registers.................................................. Tx 8 Driver Enable Registers.................................................... Tx 8 Driver Resolution Registers............................................. Tx 9 Driver Control Registers.................................................. Tx 9 Driver Enable Registers.................................................... Tx 9 Driver Resolution Registers............................................. Tx 10 Driver Control Registers................................................ Tx 10 Driver Enable Registers.................................................. Tx 10 Driver Resolution Registers........................................... 56

SPI Timing Specifications........................................................... 7 EEPROM Master I C Timing Specifications............................ 8

RESET Timing Specifications..................................................... 9 Absolute Maximum Ratings..................................................... 10 Thermal Resistance.................................................................... 10 ESD Caution................................................................................ 10 Pin Configuration and Function Descriptions........................... 11 Typical Performance Characteristics........................................... 13 Standard Test............................................................................... 17 Equalization Test........................................................................ 18 Preemphasis Test........................................................................ 20 Test Circuits..................................................................................... 22 Theory of Operation...................................................................... 23 Introduction................................................................................ 23 Receivers...................................................................................... 24 Switch Core................................................................................. 26 Transmitters................................................................................ 27 Preemphasis/Deemphasis Support for Legacy Rates............. 33 Load from Memory.................................................................... 34 I2C Serial Control Interface........................................................... 37 I2C Data Write............................................................................. I C Data Read.............................................................................. 38

SPI Serial Control Interface........................................................... 39 Write Operation.......................................................................... 39 Read Operation........................................................................... 39 Applications Information.............................................................. 40 Applications Circuit................................................................... 41 Power Consumption.................................................................. 41 Printed Circuit Board (PCB) Layout Guidelines................... 42 Register Map.................................................................................... 44

Tx 11 Driver Control Tx 11 Driver Enable Tx 11 Driver Resolution Rx 5 Active and Passive Equalization Control Rx 0 Enable Control Rx 0 Equalizer Enable Control Rx 0 LOS Enable Control Rx 0 LOS Time Control Rx 0 LOS Status Rx 0 LOS Sticky Status Rx 0 LOS Assert and Deassert Level Control Rx 0 LOS IRQ Enable Rx 11 Active and Passive Equalization Control Rx 6 Enable Control Rx 6 Equalizer Enable Control Rx 6 LOS Enable Control Rx 6 LOS Time Control Rx 6 LOS Status Register............................................66

Rx 6 LOS Sticky Status Register................................. Rx 6 LOS Assert and Deassert Level Control Register......................................................................................... Rx 6 LOS IRQ Enable Register.................................. 67 Rx Offset Calibration Control Registers.................................. 67 XPT Map A Tx Lane Select Registers....................................... 68 XPT Map B Tx Lane Select Registers....................................... 69 XPT Map C Tx Lane Select Registers....................................... 70 XPT Map D Tx Lane Select Registers...................................... 71 XPT Map Tx Lane Status Registers.......................................... 73 Boot from EEPROM Control Register..................................... 74 XPT Table Selection Control Register...................................... 74 Update XPT Table Register........................................................ 74 EEPROM Checksum Register................................................... 75 EEPROM Status Register........................................................... 75 Revision ID Register................................................................... 75 Chip ID Register......................................................................... 75 Packaging and Ordering Information.......................................... 76 Outline Dimensions................................................................... 76 Ordering Guide........................................................................... 76

Feature

Applications

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