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AD9523-1 72-Lead LFCSP (10mm x 10mm w/ EP)
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AD9523-1

Low Jitter Clock Generator With 14 LVPECL/LVDS/HSTL/29 LVCMOS Outputs

Manufacturer :
Analog Devices, Inc
Package/Case :
72-Lead LFCSP (10mm x 10mm w/ EP)
Product Categories :
Timing Circuits , Clock Generators
Datasheet:
AD9523-1 PDF
RoHs Status:
Lead free / RoHS Compliant
In-stock:
4074

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AD9523-1 Product Details

Low Jitter Clock Generator With 14 LVPECL/LVDS/HSTL/29 LVCMOS Outputs The AD9523-1 provides a low power, multi-output, clock distribution function with low jitter performance, along with an on-chip PLL and VCO with two VCO dividers. The on-chip VCO tunes from 2.94 GHz to 2.96 GHz. The AD9523-1 is defined to support the clock requirements for long term evolution (LTE) and multicarrier GSM base station designs. It relies on an external VCXO to provide the

Low Jitter Clock Generator with 14 LVPECL/LVDS/HSTL/29 LVCMOS Outputs AD9523-1
FEATURES

Output frequency: <1 MHz to 1 GHz Start-up frequency accuracy: <�100 ppm (determined by VCXO reference accuracy) Zero delay operation Input-to-output edge timing: <150 ps Dual VCO dividers 14 outputs: configurable LVPECL, LVDS, HSTL, and LVCMOS 14 dedicated output dividers with jitter-free adjustable delay Adjustable delay: 63 resolution steps of � period of VCO output divider Output-to-output skew: <50 ps Duty cycle correction for odd divider settings Automatic synchronization of all outputs on power-up Absolute output jitter: at 122.88 MHz Integration range: 12 kHz to 20 MHz Broadband timing jitter: 124 fs Digital lock detect Nonvolatile EEPROM stores configuration settings SPI- and I�C-compatible serial control port Dual PLL architecture PLL1 Low bandwidth for reference input clock cleanup with external VCXO Phase detector rate of 300 kHz to 75 MHz Redundant reference inputs Auto and manual reference switchover modes Revertive and nonrevertive switching Loss of reference detection with holdover mode Low noise LVCMOS output from VCXO used for RF/IF synthesizers PLL2 Phase detector rate to 250 MHz Integrated low noise VCO

REFA, REFA REFB, REFB REF_TEST 5 8 OUTPUTS
CONTROL INTERFACE (SPI AND I 2C) ZERO DELAY EEPROM

The AD9523-1 provides a low power, multi-output, clock distribution function with low jitter performance, along with an on-chip PLL and VCO with two VCO dividers. The on-chip VCO tunes from 2.94 GHz to 2.96 GHz. The AD9523-1 is defined to support the clock requirements for long term evolution (LTE) and multicarrier GSM base station designs. It relies on an external VCXO to provide the reference jitter cleanup to achieve the restrictive low phase noise requirements necessary for acceptable data converter SNR performance. The input receivers, oscillator, and zero delay receiver provide both single-ended and differential operation. When connected to a recovered system reference clock and a VCXO, the device generates 14 low noise outputs with a range of 1 MHz to 1 GHz, and one dedicated buffered output from the input PLL (PLL1). The frequency and phase of one clock output relative to another clock output can be varied by means of a divider phase select function that serves as a jitter-free, coarse timing adjustment in increments that are equal to half the period of the signal coming out of the VCO. An in-package EEPROM can be programmed through the serial interface to store user-defined register settings for power-up and chip reset.

APPLICATIONS

LTE and multicarrier GSM base stations Wireless and broadband infrastructure Medical instrumentation Clocking high speed ADCs, DACs, DDSs, DDCs, DUCs, MxFEs Low jitter, low phase noise clock distribution Clock generation and translation for SONET, 10Ge, 10G FC, and other 10 Gbps protocols Forward error correction (G.710) High performance wireless transceivers ATE and high performance instrumentation

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 �2010 Analog Devices, Inc. All rights reserved.

Features.............................................................................................. 1 Applications....................................................................................... 1 Functional Block Diagram.............................................................. 1 General Description......................................................................... 1 Revision History............................................................................... 2 Specifications..................................................................................... 3 Conditions..................................................................................... 3 Supply Current.............................................................................. 3 Power Dissipation......................................................................... 5 REFA, REFB, OSC_IN, and ZD_IN, ZD_IN Input Characteristics....................................... 6 OSC_CTRL Output Characteristics.......................................... 6 REF_TEST Input Characteristics............................................... 6 PLL1 Output Characteristics...................................................... OUT13, OUT13 Distribution Output Characteristics.............................................................................. 7 Timing Alignment Characteristics............................................. 8 Jitter and Noise Characteristics.................................................. 9 PLL2 Characteristics.................................................................... 9 Logic Input Pins--PD, SYNC, RESET, EEPROM_SEL, REF_SEL........................................................................................ 9 Status Output STATUS0............................. 10 Serial Control Port--SPI Mode................................................ 10 Serial Control Port--I2C Mode................................................ 11 Absolute Maximum Ratings.......................................................... 12 Thermal Resistance.................................................................... 12 ESD Caution................................................................................ 12 Pin Configuration and Function Descriptions........................... 13 Typical Performance Characteristics........................................... 16 Input/Output Termination Recommendations.......................... 19 Terminology.................................................................................... 20 Theory of Operation...................................................................... 21 Detailed Block Diagram............................................................ 21 Overview..................................................................................... 21 Component Blocks--Input PLL (PLL1).................................. 22 Component Blocks--Output PLL (PLL2).............................. 23 Clock Distribution..................................................................... 25 Zero Delay Operation................................................................ 27 Serial Control Port......................................................................... 28 SPI/I2C Port Selection................................................................ 28 I2C Serial Port Operation.......................................................... 28 SPI Serial Port Operation.......................................................... 31 SPI Instruction Word (16 Bits)................................................. 32 SPI MSB/LSB First Transfers.................................................... 32 EEPROM Operations..................................................................... 35 Writing to the EEPROM........................................................... 35 Reading from the EEPROM..................................................... 35 Programming the EEPROM Buffer Segment......................... 35 Power Dissipation and Thermal Considerations....................... 37 Clock Speed and Driver Mode................................................. 37 Evaluation of Operating Conditions........................................ 37 Thermally Enhanced Package Mounting Guidelines............ 38 Control Registers............................................................................ 39 Control Register Map................................................................ 39 Control Register Map Bit Descriptions................................... 44 Outline Dimensions....................................................................... 57 Ordering Guide.......................................................................... 57

fVCXO = 122.88 MHz single-ended, REFA and REFB on differential at 30.72 MHz, fVCO = 2949.12 MHz, doubler is on, unless otherwise noted. Typical is given for VDD � 5%, and = 25�C, unless otherwise noted. Minimum and maximum values are given over the full VDD and to +85�C) variation, as listed in Table 1.

Parameter SUPPLY VOLTAGE VDD3_PLL, Supply Voltage for PLL1 and PLL2 VDD3_VCO, Supply Voltage for VCO VDD3_REF, Supply Voltage Clock Output Drivers Reference VDD3_OUT[x:y], 1 Supply Voltage Clock Output Drivers VDD1.8_OUT[x:y],1 Supply Voltage Clock Dividers TEMPERATURE RANGE, TA

x and y are the pair of differential outputs that share the same power supply. For example, VDD3_OUT[0:1] is Supply Voltage Clock Output OUT0, OUT0 (Pin 68 and Pin 67, respectively) and Supply Voltage Clock Output OUT1, OUT1 (Pin 65 and Pin 64, respectively).

Parameter SUPPLIES OTHER THAN CLOCK OUTPUT DRIVERS VDD3_PLL, Supply Voltage for PLL1 and PLL2 VDD3_VCO, Supply Voltage for VCO and VCO Divider M1 VDD3_REF, Supply Voltage Clock Output Drivers Reference VCO Divider M1 Enabled LVPECL Mode, LVDS Mode Min Typ 37 70 Max 41.9 75.8 Unit mA Test Conditions/Comments Decreases 9 mA typical if REFB is turned off All outputs use VCO Divider M1

HSTL Mode, CMOS Mode VCO Divider M2 Enabled LVPECL Mode, LVDS Mode

Use VCO Divider M1; only one output driver is turned on; for each additional output that is turned on, the current increments 1.2 mA maximum Use VCO Divider M1; values are independent of the number of outputs turned on Use VCO Divider M2; only one output driver is turned on; for each additional output that is turned on, the current increments 1.2 mA maximum Use VCO Divider M2; values are independent of the number of outputs turned on Current for each divider: = 122.88 MHz Current for each divider: = 983.04 MHz Channel x control register, Bit 122.88 MHz = 983.04 MHz = 122.88 MHz = 983.04 MHz = 122.88 MHz = 983.04 MHz

HSTL Mode, CMOS Mode VDD1.8_OUT[x:y], 1 Supply Voltage Clock Dividers VDD1.8_OUT[x:y],1 Supply Voltage Clock Dividers CLOCK OUTPUT DRIVERS--LOWER POWER MODE OFF LVDS Mode, mA VDD3_OUT[x:y],1 Supply Voltage Clock Output Drivers VDD3_OUT[x:y],1 Supply Voltage Clock Output Drivers LVDS Mode, mA VDD3_OUT[x:y],1 Supply Voltage Clock Output Drivers VDD3_OUT[x:y],1 Supply Voltage Clock Output Drivers LVPECL Mode VDD3_OUT[x:y],1 Supply Voltage Clock Output Drivers VDD3_OUT[x:y],1 Supply Voltage Clock Output Drivers


Feature

  • Output frequency: <1 MHz to 1 GHz
  • Start-up frequency accuracy: <±100 ppm (determined by VCXO reference accuracy)
  • Zero delay operationInput-to-output edge timing: <150 ps
  • Dual VCO dividers
  • 14 outputs: configurable LVPECL, LVDS, HSTL, and LVCMOS
  • 14 dedicated output dividers with jitter-free adjustable delay
  • Adjustable delay: 63 resolution steps of ½ period of VCO output divider
  • Output-to-output skew: <50 ps
  • Duty cycle correction for odd divider settings
  • Automatic synchronization of all outputs on power-up
  • Absolute output jitter: <150 fs at 122.88 MHz Integration range: 12 kHz to 20 MHz
  • See data sheet for additional features

AD9523-1 Pinout
(Picture: Pinout)

AD9523-1 Block Diagram
(Picture: Diagram)

Technical Parameters

# Outputs 14 Output Logic HSTL, LVCMOS, LVDS, LVPECL
Clock Function Generation Powertyp | W 898m
Interface I²C, Serial, SPI Ref Clockmax | Hz 400M
On Chip VCO or DCO Yes Ref Clockmin | Hz -
Output Frequencymax | Hz 1G

AD9523-1 Documents

  • AD9523-1 Technical Documentation/Data sheet

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