2-Channel Dual ADC Pipelined 3Gsps 14-bit JESD204B 196-Pin TEBGA Tray
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AD9208BBPZ-3000 Product Details
The AD9208BBPZ-3000 is a dual, 14-bit, 3 GSPS analog-to-digital converter (ADC). The device has an on-chip buffer and a sample-and-hold circuit designed for low power, small size, and ease of use. This product is designed to support communications applications capable of direct sampling wide bandwidth analog signals of up to 5 GHz. The −3 dB bandwidth of the ADC input is 9 GHz. The AD9208BBPZ-3000 is optimized for wide input bandwidth, high sampling rate, excellent linearity, and low power in a small package.
The dual ADC cores feature a multistage, differential pipelined architecture with integrated output error correction logic. Each ADC features wide bandwidth inputs supporting a variety of user-selectable input ranges. An integrated voltage referenceeases design considerations. The analog input and clock signals are differential inputs. The ADC data outputs are internally connected to four digital downconverters (DDCs) through a crossbar mux. Each DDC consists of up to five cascaded signalprocessing stages: a 48-bit frequency translator (numerically controlled oscillator (NCO)), and up to four half-band decimationfilters. The NCO has the option to select preset bands over the general-purpose input/output (GPIO) pins, which enables the selection of up to three bands. Operation of the AD9208BBPZ-3000 between the DDC modes is selectable via SPI-programmable profiles.
In addition to the DDC blocks, the AD9208BBPZ-3000 has several functions that simplify the automatic gain control (AGC) function in acommunications receiver. The programmable threshold detector allows monitoring of the incoming signal power using the fast detect control bits in Register 0x0245 of the ADC. If the input signal level exceeds the programmable threshold, the fast detect indicator goes high. Because this threshold indicator has low latency, the user can quickly turn down the system gain to avoidan overrange condition at the ADC input. In addition to the fast detect outputs, the AD9208BBPZ-3000 also offers signal monitoring capability. The signal monitoring block provides additional information about the signal being digitized by the ADC.
The user can configure the Subclasss 1 JESD204B-based high speed serialized output in a variety of one-lane, two-lane, four-lane, and eight-lane configurations, depending on the DDC configuration and the acceptable lane rate of the receiving logic device. Multidevice synchronization is supported through the SYSREF± and SYNCINB± input pins.
The AD9208BBPZ-3000 has flexible power-down options that allow significant power savings when desired. All of these features canbe programmed using a 3-wire serial port interface (SPI).
The AD9208BBPZ-3000 is available in a Pb-free, 196-ball BGA, specified over the −40°C to +85°C ambient temperature range. Thisproduct is protected by a U.S. patent.
Note that throughout this data sheet, multifunction pins, such as FD_A/GPIO_A0, are referred to either by the entire pin name or by a single function of the pin, for example, FD_A, when only that function is relevant.
- JESD204B (Subclass 1) coded serial digital outputs
- Support for lane rates up to 16 Gbps per lane
- 1.65 W total power per channel at 3 GSPS (default settings)
- Performance at −2 dBFS amplitude, 2.6 GHz input
- SFDR = 70 dBFS
- SNR = 57.2 dBFS
- Performance at −9 dBFS amplitude, 2.6 GHz input
- SFDR = 78 dBFS
- SNR = 59.5 dBFS
- Integrated input buffer
- Noise density = −152 dBFS/Hz
- 0.975 V, 1.9 V, and 2.5 V dc supply operation
- 9 GHz analog input full power bandwidth (−3 dB)
- Amplitude detect bits for efficient AGC implementation
- 2 integrated, wideband digital processors per channel
- 48-bit NCO
- 4 cascaded half-band filters
- Phase coherent NCO switching
- Up to 4 channels available
- Serial port control
- Integer clock with divide by 2 and divide by 4 options
- Flexible JESD204B lane configurations
- On-chip dither
- Diversity multiband, multimode digital receivers
- 3G/4G, TD-SCDMA, W-CDMA, GSM, LTE, LTE-A
- Electronic test and measurement systems
- Phased array radar and electronic warfare
- DOCSIS 3.0 CMTS upstream receive paths
- HFC digital reverse path receivers
- Number of Bits
- Sampling Rate (Per Second)
- Number of Inputs
- Input Type
- Data Interface
- Number of A/D Converters
- Reference Type
- Voltage Supply, Analog
- 0.95V ~ 1V, 1.85V ~ 1.95V, 2.44V ~ 2.56V
- Voltage Supply, Digital
- 0.95V ~ 1V, 1.85V ~ 1.95V
- Operating Temperature
- -40??C ~ 85??C
- Package / Case
- 196-LFBGA Exposed Pad
- Supplier Device Package
- 196-BGA-ED (12x12)
- Mounting Type
- Surface Mount
AD9208 Technical Documentation/Data sheet
AD9208BBPZ-3000 Related Products
Ratings and Reviews (2)
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Fast delivery 5 star.
Very good! As in the description! Thanks!
Estimated Delivery Time: Jul 02 - Jul 07 days (choose Expedited at checkout).
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1.We provide 90 days warranty.
2.If some of the items you received aren't of perfect quality, we would resiponsibly arrange your refund or replacement. But the items must remain their orginal condition.
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- The AD's inventory fluctuates greatly and cannot be updated in time, it will be updated periodically within 24 hours. After submitting an order for AD9208BBPZ-3000, it is recommended to confirm the order with Jotrin salesperson or online customer service before payment.
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- Q: What is the process for returns or replacement of AD9208BBPZ-3000?
All goods will implement Pre-Shipment Inspection (PSI), selected at random from all batches of your order to do a systematic inspection before arranging the shipment.
If there is something wrong with the AD9208BBPZ3000 we delivered, we will accept the replacement or return of the AD9208BBPZ-3000 only when all of the below conditions are fulfilled:
(1)Such as a deficiency in quantity, delivery of wrong items, and apparent external defects (breakage and rust, etc.), and we acknowledge such problems.
(2)We are informed of the defect described above within 90 days after the delivery of AD9208BBPZ-3000.
(3)The AD9208BBPZ-3000 is unused and only in the original unpacked packaging.
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(1)Inform us within 90 days
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