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82P33910-1BAG Product Details
The 82P33910-1BAG Synchronization System for IEEE 1588 is comprised of software and hardware designed to meet the needs of IEEE 1588 slave clock and master clock applications. The system includes Precision Time Protocol (PTP) stack software (Stack) and clock recovery servo software (Servo) that runs on an external processor; and Synchronization Management Unit (SMU) hardware.
The included PTP stack is IEEE 1588-2008 compliant and is used to control the exchange of messages between IEEE 1588 masters and slaves. The Servo recovers accurate and stable electrical synchronization signals from packet based references generated by IEEE 1588 masters. The Servo is capable of filtering the effects of Packet Delay Variation (PDV) often present in IEEE 1588 unaware networks.
The SMU hardware provides tools to manage timing references, clock sources and timing paths for IEEE 1588 and Synchronous Ethernet (SyncE) based clocks. The device supports up to three independent timing paths that control: IEEE 1588 clock synthesis; SyncE clock generation; and general purpose frequency translation. The device supports physical layer timing with Digital PLLs (DPLLs) and it supports packet based timing with Digitally Controlled Oscillators (DCOs). Input-to-input, input-to-output and output-to-output phase skew can all be precisely managed. The device outputs low-jitter clocks that can directly synchronize Ethernet interfaces; as well as SONET/SDH and PDH interfaces and IEEE 1588 Time Stamp Units (TSUs).
For more information or to request documentation, please contact your local representative.
- Includes IEEE 1588-2008 compliant protocol stack, clock recovery servo software,and Synchronization Management Unit (SMU) hardware
- Implements ITU-T Telecom Profiles
- Operates as IEEE 1588 / PTP slave or master
- Recovers accurate and stable synchronization signals from packet based IEEE 1588 / PTP master
- Reference trackers filter packet synchronization noise from IEEE 1588 unaware networks
- PTP clocks comply with ITU-T G8273.2 and G.8263
- Physical layer clocks comply with ITU-T G.8262 for Synchronous Ethernet Equipment Clock (EEC), and G.813 for Synchronous Equipment Clock (SEC), and Telcordia GR-253-CORE for Stratum 3 and SONET Minimum Clock (SMC)
- System-wide precise 1PPS (Pulse Per Second) time of day alignment is supported with programmable input-to-input, input-to-output and output-to-output phase delays: sub-ns resolution
- Generates clocks for: Ethernet, SONET/SDH and PDH interfaces: jitter generation <1 ps RMS (12 kHz to 20 MHz)
- Eases local oscillator sourcing by supporting any of eight common TCXO/OCXO frequencies for the System Clock: 10 MHz, 12.8 MHz, 13 MHz, 19.44 MHz, 20 MHz, 24.576 MHz, 25 MHz or 30.72 MHz
- 144 pin CABGA package
- Supported by
|PLL||Yes||Operating Temperature||-40??C ~ 85??C|
|Main Purpose||Ethernet, SONET/SDH, Stratum||Mounting Type||Surface Mount|
|Number of Circuits||3||Package / Case||144-LBGA|
|Ratio Input:Output||14:13||Supplier Device Package||144-CABGA (13x13)|
IDT 82P33910 1 DATASHEET
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Estimated Delivery Time: Dec 04 - Dec 09 days (choose Expedited at checkout).
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